# Uniform channel architecture. 

io_rat 2 
chan_width_io 1
chan_width_x uniform 1 
chan_width_y uniform 1

# 4-input LUT.  LUT inputs first, then output, then clock.
inpin class: 0 left			# LUT in 0
inpin class: 0 top			# LUT in 1
inpin class: 0 right			# LUT in 2
inpin class: 0 bottom			# LUT in 3
outpin class: 1 right bottom            # Output 
inpin class: 2 left top			# clock