This is what the LUT looks like:

                                |  |
                                |  |
                             ---+--+---
                             |  1 4?5?|
                          ---+5?4?   6+---
                             |        |
                          ---+0      2+---
                             |  3  6  |
                             |--+--+---
                                |  |
                                |  |

That is, the L blocks have 7 pins, numbered from 0 to 6.  Pins 0,1,2,3 are
look-up table inputs, 4 is the clock input the L block's flipflop, 5 is a
tristate enable and 6 is the L block output.  None of the circuits use pins
4 or 5, so their exact location is unknown.

-------------------------------------------------------------------------------
Below is the contents of an input file (cge.arch.2)
supplied to VPR to describe the FPGA architecture.
-------------------------------------------------------------------------------

# Uniform channel architecture. 

io_rat 2 
chan_width_io 1
chan_width_x uniform 1 
chan_width_y uniform 1

# 4-input LUT.  LUT inputs first, then output, then clock.
inpin class: 0 left			# LUT in 0
inpin class: 0 top			# LUT in 1
inpin class: 0 right			# LUT in 2
inpin class: 0 bottom			# LUT in 3
outpin class: 1 right bottom            # Output 
inpin class: 2 left top			# clock