TRPOS Time-Multiplexer and Packet Generator

Vaughn Betz, David Jones, Guy Lemieux, Mark Stoodley, and Ralph Wittig with the guidance of Professor Paul Chow.

TRPOS is an example of what you get when you mix five grad students and IC fab facilities with a Prof Who Assigns Grades. This integrated circuit was designed to accept a continuous raw bit stream at a rate of 10 Mb/second on multiple channels. The data is fully buffered and time-multiplexed onto 16 output channels running at 50 Mb/second. Header information is also added so the data can be packet-switched by the Starburst ATM chip (designed the year before by some grad students with the same Prof Who Assigns Grades). The IC core has capacity for 64 input channels, but only 32 channels were bonded out due to the limited number of bond pads we could place on the periphery of the core.

We received 10 chips back from the fab in March (?). One of these chips appeared to have some shorted inputs and a floating output. The other chips all functioned identically: 15 of the 16 output channels worked correctly, the other output channel was consistently erroneous. We have not been able to trace the source of the fault, but we suspect there may have been a mask generation error (since all 16 bitslices have identical layouts).

Although designed for 50 MHz operation, the chip has only been tested to run at output speeds of 20 MHz due to tester limitations. Some day, when we have access to a better tester, we may run it at the full 50 MHz (yeah, right). Until then, we'll believe our detailed Spice simulations.

We started the project in January, 1994. By the end of February, we had the architecture defined and some schematics entered. By the end of March, we were beginning to make layout and floorplan decisions. The last layout change was made May 26 and simulation results finished by May 28. On May 31, at 4:57pm, we frantically rushed to the prof's office to submit the final report only to find he hadn't come in on that day.

We submitted the chip to fab in June as a "Last Minute Club" member, which means we get on the run if there's space left (multiple designs are squeezed into one large reticle, which is step & repeated across the wafer) or somebody else who has a reservation misses their deadline. However, our large die size gave us little hope of making that fab run. We were turned down, so we applied for a reservation on the October?November? run. Obviously, we were successful and got packaged chips back in March?. Our tester accepted 96-pin PGAs but our chip was bonded out onto a 120-pin PGA, so we spent a month digging for scrap components and building a testing adapter jig. It turns out our jig was the source of numerous phantom errors during testing, mostly due to poor contacts. We managed to minimize these by using brute force (it was tempting to use big C-clamps and a hammer :-).

Reports

: Course Report on the Architecture ( PostScript)
: Course Report on our CAD Tool Setup and Environment. ( PostScript) All chips previously fabbed by UofT in CMOS were designed using Cadence Edge. We were the first to use Cadence Design Framework II, so much effort was needed just to debug the CMOS libraries and start a CAD process flow.

Pictures

Publications

: A 64 x 10 Mb/s to 16 x 50 Mb/s Area-Efficient Time-Domain Multiplexer and Packetizer
(PDF) (PostScript)