My Publications
This page includes all my publication divided in three sections by following the instructions for the preparation of the tenure documentation.
6 Most Important Contributions
The reviewer may notice that I didn’t include in the list of the most important contributions some work with a much greater number of citations compared to the one reported. This choice was done to highlight the most recent achievements reached during my activity at the University of Toronto. The choice of the 6 most important contributions was performed upon the following criteria:
- 3 journal papers and 3 conference papers
- 2 publications published as Associate Professor at the University of Toronto, 2 publications as Assistant Professor at the University of Toronto and 2 publications chosen from the entire portfolio.
[J.1] J. Musayev and A. Liscidini, "A Quantized Analog RF Front End," in IEEE Journal of Solid-State Circuits, vol. 54, no. 7, pp. 1929-1940, July 2019. [PDF]
The paper is focused on quantized-analog signal processing. This concept allows to merge digital and analog domain seamlessly improving power efficiency and flexibility of traditional design. This concept led to a patent [P.1] and it is at the basis of several ongoing activities that involve several areas such as, SAW-less transceivers, cryogenic interfaces, analog accelerators processors, RF-Opto interfaces.
[J.2] A. Pathan, A. Liscidini, “Thermal noise limit for time domain analog signal processing in CMOS technologies” Electronic Letters, vol. 52, no.18, pp.1567,1568, February 2016 [PDF]
The paper is focused on the fundamental limitations in time domain analog signal processing. The importance of this work has been also recognized by Electronic Letter, which dedicated a “feature article” in front of the issue where the paper is published.
[J.3] A. Selvakumar, M. Zargham, and A. Liscidini, "Sub-mW Current Re-Use Receiver Front-End for Wireless Sensor Network Applications," IEEE Journal of Solid-State Circuits, vol. 50, Issue 12, pp. 2965-2974, 2015. [PDF]
This paper is representative of my research on ultra-low-power RX, At the time of its publication at ISSCC it was the lowest power BLE RF front-end receiver ever reported. It was then invited on the JSSC Special issue dedicated on the most significant works of ISSCC 2015
[C.1] Z. Ji, S. Zargham and A. Liscidini, "Low-Power QPSK Transmitter Based on an Injection-Locked Power Amplifier," ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC), Dresden, 2018, pp. 134-137. (Best Student Paper Award - as supervisor) [PDF]
This paper, presented at ESSCIRC2018, shows exploit the properties of injection locking dividers to be used as power efficient phase modulators. The paper, in the area of frequency synthesis, was very well received and won the Best Student Paper Award of the conference (the only award of the entire conference). An extended version has been also published recently on JSSC [J.4].
[C.2] L. Vercesi, L. Fanori, F. De Bernardinis, A. Liscidini, R. Castello, " A Dither-less All Digital PLL for Cellular Transmitters," IEEE Custom Integrated Circuits Conference, 2011. (CICC), Sept. 2011 (Best invited paper award CICC2011 – presented by A. Liscidini) [PDF]
This paper represents my early achievements in the area of time domain signal processing. It was very welcome by the conference and as presenting author I received the best invited paper award. The paper was then invited on the JSSC Special issue dedicated on the most significant works of CICC2011 [J.19]
[C.3] A. Liscidini, M. Brandolini, D. Sanzogni, R. Castello, "A 0.13 _m CMOS front-end for DCS1800/UMTS/802.11b-g with multi-band positive feedback low noise amplifier," Digest of Technical Papers Symposium on VLSI Circuits, (VLSI) 2005, pp. 406- 409, 16-18 June 2005
(Best student paper award VLSI2005 – presented by A. Liscidini) [PDF]
This paper represents my earliest achievement in the area RF wireless receivers. It was very welcome by the conference and as presenting author I received the best student paper award. The paper was then invited on the JSSC Special issue dedicated on the most significant works of VLSI2005 [J.28]
Other Full referred Journal
[J.4] S. Zargham, Z. Ji and A. Liscidini, "A 2.4-GHz 1.3-mW OQPSK RF Front-End TX Based on an Injection-Locked Power Amplifier," in IEEE Journal of Solid-State Circuits, vol. 56, no. 5, pp. 1541-1552, May 2021. [PDF]
[J.5] T. Haapala, A. Liscidini and K. A. I. Halonen, "Temperature Compensation of Crystal References in NB-IoT Modems," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 7, pp. 2467-2480, July 2020. [PDF]
[J.6] K.Vasilakopoulos, A. Liscidini, “A Reconfigurable Passive Switched-Capacitor TX RF Front End With −57 dB ACLR2” IEEE Solid-State Circuits Letters, 3 , pp. 294-297, 2020. [PDF]
[J.7] S. Z. Lüleç, D. A. Johns and A. Liscidini, "A Third-Order Integrated Passive Switched-Capacitor Filter Obtained With a Continuous-Time Design Approach," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 10, pp. 3643-3652, 2019 [PDF]
[J.8] J. Musayev and A. Liscidini, "Quantised inverter amplifier," in Electronics Letters, vol. 54, no. 7, pp. 416-418, 5 4 2018. [PDF]
[J.9] Q. Wang, H. Shibata, A. Liscidini and A. C. Carusone, "A Digital Filtering ADC With Programmable Blocker Cancellation for Wireless Receivers," in IEEE Journal of Solid-State Circuits, vol. 53, no. 3, pp. 681-691, March 2018. [PDF]
[J.10] S. Z. Lulec; D. Johns; A. Liscidini, "A Simplified Model for Passive Switched-Capacitor Filters with Complex Poles," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol.63, no.6, pp.513-517, June 2016 [PDF]
[J.11] C. Li, A. Liscidini, "Class-C PA-VCO Cell for FSK and GFSK Transmitters", IEEE Journal of Solid-State Circuits, vol. 51, Issue 7, pp. 1537-1546, 2016 [PDF]
[J.12] A. Liscidini, "Fundamentals of Modern RF Wireless Receivers: A Short Tutorial," in IEEE Solid-State Circuits Magazine, vol. 7, no. 2, pp. 39-48, Spring 2015. [PDF]
[J.13] Selvakumar, A., Liscidini, A., "Current-Recycling Complex Filter for Bluetooth-Low-Energy Applications," IEEE Transactions on Circuits and Systems II: Express Briefs, vol.62, no.4, pp.332,336, April 2015 [PDF]
[J.14] Codega, N.; Rossi, P.; Pirola, A.; Liscidini, A.; Castello, R., "A Current-Mode, Low Out-of-Band Noise LTE Transmitter With a Class-A/B Power Mixer," IEEE Journal of Solid-State Circuits, vol.49, no.7, pp.1627,1638, July 2014 [PDF]
[J.15] M. Garampazzi, S. Dal Toso, A. Liscidini, D. Manstretta, P. Mendez, L. Romano, R. Castello, "An Intuitive Analysis of Phase Noise Fundamental Limits Suitable for Benchmarking LC Oscillators," IEEE Journal of Solid-State Circuits, vol.49, no.3, pp.635-645, March 2014 [PDF]
[J.16] A. Liscidini, L. Fanori, P. Andreani, R. Castello, "A Power-Scalable DCO for Multi-Standard GSM/WCDMA Frequency Synthesizers," IEEE Journal of Solid-State Circuits, vol.49, no.3, pp.646-656, March 2014 [PDF]
[J.17] I. Fabiano, M. Sosio, A. Liscidini, R. Castello, "SAW-Less Analog Front-End Receivers for TDD and FDD," IEEE Journal of Solid-State Circuits, vol.48, no.12, pp.3067-3079, Dec. 2013 [PDF]
[J.18] M. Sosio, A. Liscidini, R. Castello, “An Intuitive Current-Driven Passive Mixer Model Based on Switched-Capacitor Theory" IEEE Transactions on Circuits and Systems II: Express Briefs, no. 2, pp. 66–70, Feb. 2013 [PDF]
[J.19] L. Vercesi, L. Fanori, F. De Bernardinis, A. Liscidini, R. Castello, " A Dither-Less All Digital PLL for Cellular Transmitters" IEEE Journal of Solid-State Circuits, vol.47, no.8, pp.1908-1920, Aug. 2012 [PDF]
[J.20] L. Ping, A. Liscidini, P. Andreani, " A 3.6 mW, 90 nm CMOS Gated-Vernier Time-to-Digital Converter With an Equivalent Resolution of 3.2 ps", IEEE Journal of Solid-State Circuits, vol.47, no.7, pp.1626-1635, Apr. 2012 [PDF]
[J.21] M. Sosio, A. Liscidini, R. Castello, "A 2G/3G Cellular Analog Baseband Based on a Filtering ADC," IEEE Transactions on Circuits and Systems II: Express Briefs, vol.59, no.4, pp.214-218, Apr. 2012 [PDF]
[J.22] L. Fanori, A. Liscidini, R. Castello, "Capacitive Degeneration in LC-Tank Oscillator for DCO Fine-Frequency Tuning," IEEE Journal of Solid-State Circuits, vol.45, no.12, pp.2737-2745, Dec. 2010 [PDF]
[J.23] A. Pirola, A. Liscidini, R. Castello, "Current-Mode, WCDMA Channel Filter With In-Band Noise Shaping," IEEE Journal of Solid-State Circuits, vol.45, no.9, pp.1770-1780, Sept. 2010 [PDF]
[J.24] M. Tedeschi, A. Liscidini, R. Castello, "Low-Power Quadrature Receivers for ZigBee (IEEE 802.15.4) Applications," IEEE Journal of Solid-State Circuits, vol.45, no.9, pp.1710-1719, Sept. 2010 [PDF]
[J.25] L. Vercesi, A. Liscidini, R. Castello, "Two-Dimensions Vernier Time-to-Digital Converter," IEEE Journal of Solid-State Circuits, vol.45, no.8, pp.1504-1512, Aug. 2010 [PDF]
[J.26] A. Liscidini, G. Martini, D. Mastantuono, R. Castello, "Analysis and Design of Configurable LNAs in Feedback Common-Gate Topologies," IEEE Transactions on Circuits and Systems II: Express Briefs, vol.55, no.8, pp.733-737, Aug. 2008 [PDF]
[J.27] A. Liscidini, A. Mazzanti, R. Tonietto, L. Vandi, P. Andreani, R. Castello, "Single-Stage Low-Power Quadrature RF Receiver Front-End: The LMV Cell," IEEE Journal of Solid-State Circuits, vol.41, no.12, pp.2832-2841, Dec. 2006 [PDF]
[J.28] A. Liscidini, M. Brandolini, D. Sanzogni, R. Castello, "A 0.13 _m CMOS front-end, for DCS1800/UMTS/802.11b-g with multiband positive feedback low-noise amplifier," IEEE Journal of Solid-State Circuits, vol.41, no.4, pp. 981- 989, April 2006 [PDF]
[J.29] P. Rossi, A. Liscidini, M. Brandolini, F. Svelto, "A variable gain RF front-end, based on a Voltage-Voltage feedback LNA, for multistandard applications," IEEE Journal of Solid-State Circuits, vol.40, no.3, pp. 690- 697, March 2005 [PDF]
Other Referred Conferences
[C.4] A. Khakpour, A.Liscidini, "Thermodynamics limits in Oscillators and Phase Locked Loops" (invited paper) ICFN 2019, Lausanne, (June 2019). [PDF]
[C.5] J. Musayev and A. Liscidini, "Quantized Analog RX Front-End for SAW-Less Applications," ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC), Dresden, 2018, pp. 306-309. [PDF]
[C.6] Z. Jiang, D. A. Johns and A. Liscidini, "A low-power sub-GHz RF receiver front-end with enhanced blocker tolerance," 2018 IEEE Custom Integrated Circuits Conference (CICC), San Diego, CA, 2018, pp. 1-4. [PDF]
[C.7] Q. Wang, H. Shibata, A. C. Carusone and A. Liscidini, "A LTE RX front-end with digitally programmable multi-band blocker cancellation in 28nm CMOS," 2017 IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, 2017, pp. 1-4. [PDF]
[C.8] S. Z. Lulec, D. A. Johns and A. Liscidini, "A 150-uW 3rd-order butterworth passive-switched-capacitor filter with 92 dB SFDR," 2017 Symposium on VLSI Circuits (VLSI), Kyoto, 2017, pp. C142-C143. [PDF]
[C.9] Q. Wang, A. Liscidini and A. C. Carusone, "Filtering ADCs for wireless receivers: A survey," 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), Boston, MA, 2017, pp. 997-1000. [PDF]
[C.10] T. Liu, A. Liscidini, “A 1.92 mW Filtering Transimpedance Amplifier for RF Current Passive Mixers” 2016 IEEE International Solid- State Circuits Conference (ISSCC) pp. 358-359 Feb. 2016 [PDF]
[C.11] C. Li, A. Liscidini, "A Current Re-Use Pa-VCO Cell for Low-Power BLE Transmitters" Proceedings of the ESSCIRC, 2015, pp.183,186, Sept. 2015. [PDF]
[C.12] A. Pipino, A. Liscidini, K. Wan and A. Baschirotto, "Bluetooth low energy receiver system design," 2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, 2015, pp. 465-468 [PDF]
[C.13] A Selvakumar, M. Zargham, A. Liscidini, "13.6 A 600_W Bluetooth low-energy front-end receiver in 0.13_m CMOS technology," 2015 IEEE International Solid- State Circuits Conference (ISSCC) , pp.1,3, 22-26 Feb. 2015 [PDF]
[C.14] N. Codega, A. Liscidini, R. Castello, “A Low Out-of-Band Noise LTE Transmitter with Current-Mode Approach”, Proceedings of the ESSCIRC, 2013, pp.283,286, Sept. 2013. [PDF]
[C.15] P. Lu, P. Andreani, A. Liscidini, “A 2-D GRO Vernier Time-to-Digital Converter with Large Input Range and Small Latency” IEEE RFIC Digest of Technical Papers, Seattle, Washington, USA, June 2013 [PDF]
[C.16] I. Fabiano, M. Sosio, A. Liscidini, R. Castello, " SAW-less analog front-end receivers for TDD and FDD," IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 pp. 83, Feb. 2013 [PDF]
[C.17] P. Rossi, N. Codega, D. Gerna, A. Liscidini, D. Ottini, Y. He, A. Pirola, E. Sacchi, G. Uehara, C. Yang, R. Castello, " An LTE Transmitter Using a Class-A/B Power Mixer," IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 pp. 341, Feb. 2013 [PDF]
[C.18] A. Liscidini, L. Fanori, P. Andreani, R.Castello, " A 36mW/9mW Power-Scalable DCO in 55nm CMOS for GSM/WCDMA Frequency Synthesizers," IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 pp. 348, Feb. 2012. [PDF]
[C.19] L. Fanori, A. Liscidini, P. Andreani, " A 6.7-9.2GHz 65nm CMOS hybrid class-B/class-C cellular TX VCO" IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 354, Feb 2012. [PDF]
[C.20] P. Lu, P. Andreani, A. Liscidini, "A 90nm CMOS gated-ring-oscillator-based Vernier time-to-digital converter for DPLLs," Proceedings of the ESSCIRC (ESSCIRC), 2011, pp.459-462, 12-16 Sept. 2011. [PDF]
[C.21] M. Sosio, A. Liscidini, R. Castello, F. De Bernardinis, "A complete DVB-T/ATSC tuner analog base-band implemented with a single filtering ADC," Proceedings of the ESSCIRC (ESSCIRC), 2011 pp.391-394, 12-16 Sept. 2011. [PDF]
[C.22] L. Fanori, A. Liscidini, R. Castello, "3.3GHz DCO with a frequency resolution of 150Hz for All-digital PLL," IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010, pp.48-49, 7-11 Feb. 2010. [PDF]
[C.23] A. Liscidini, A. Pirola, R. Castello, "A 1.25mW 75dB-SFDR CT filter with in-band noise reduction," IEEE International Solid-State Circuits Conference Digest of Technical Papers, (ISSCC) 2009, pp.336-337, 8-12 Feb. 2009 [PDF]
[C.24] A. Liscidini, L. Vercesi, R. Castello, "Time to digital converter based on a 2-dimensions Vernier architecture," IEEE Custom Integrated Circuits Conference, 2009 (CICC), pp.45-48, 13-16 Sept. 2009 [PDF]
[C.25] A. Liscidini, "Single-stage RF quadrature front-end receivers for ultra-low power applications," International Conference on Microelectronics, 2008. ICM 2008, pp.304,307, 14-17 Dec. 2008 [PDF]
[C.26] A. Liscidini, M. Tedeschi, R. Castello, "A 2.4 GHz 3.6mW 0.35mm2 Quadrature Front-End RX for ZigBee and WPAN Applications," IEEE International Solid-State Circuits Conference Digest of Technical Papers, (ISSCC) 2008, pp. 370-620, 3-7 Feb. 2008 [PDF]
[C.27] M. Tedeschi, A. Liscidini, R. Castello, "A 0.23mm2 free coil ZigBee receiver based on a bond-wire self-oscillating mixer," Proceedings of the ESSCIRC (ESSCIRC) 2008, pp.430-433, 15-19 Sept. 2008 [PDF]
[C.28] A. Liscidini, C. Ghezzi, E. Depaoli, G. Albasini, I. Bietti, R. Castello, "Common Gate Transformer Feedback LNA in a High IIP3 Current Mode RF CMOS Front-End," IEEE Custom Integrated Circuits Conference, 2006 (CICC), pp.25-28, 10-13 Sept. 2006 [PDF]
[C.29] A. Liscidini, A. Mazzanti, R. Tonietto, L. Vandi, P. Andreani, R. Castello, "A 5.4mW GPS CMOS Quadrature Front-End Based on a Single-Stage LNA-Mixer-VCO," IEEE International Solid-State Circuits Conference Digest of Technical Papers, (ISSCC) 2006, pp.1892-1901, 6-9 Feb. 2006 [PDF]
[C.30] A. Liscidini, M. Brandolini, P. Rossi, F. Torrisi, F. Svelto, "Design methodology of feedback-LNAs for GHz applications," Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, (BCTM) 2004, pp. 253- 256, 13-14 Sept. 2004. [PDF]
[C.31] P. Rossi, A. Liscidini, M. Brandolini, F. Svelto, "A 2.5dB NF direct-conversion receiver front-end for HiperLAN2/IEEE802.11a," IEEE International Solid-State Circuits Conference Digest of Technical Papers, (ISSCC) 2004, pp. 102- 516 Vol.1, 15-19 Feb. 2004 [PDF]