myself
Welcome
Martin Labrecque
http://z.about.com/d/webclipart/1/0/q/O/1/un1.gif - 3.7 K

library
Who
Publications
Contact
Links
Who:
Since Fall 2003, I have been a graduate applied science student at the University of Toronto. I currently work with Professor Steffan, with whom I completed my Masters's on network processors. Although I have done a lot of litterature review on this topic, it is unclear to me if I should publish any of that in here. My doctorate program started in 2005. Computer architecture at large, including compiler support, is also of interest to me. I was born in Laval, Quebec.

Recent publications:

  • Application-Specific Signatures for Transactional Memory in Soft Processors, (bibtex) Martin Labrecque, Mark Jeffrey and J. Gregory Steffan. ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 4 Issue 3, August 2011

  • NetTM: Faster and Easier Synchronization for Soft Multicores via Transactional Memory, (pdf, ps, pdf slides, bibtex) Martin Labrecque and J. Gregory Steffan, Nineteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), Monterey, California, February, 2011.
    • NetTM Website: Wiki
    • Overview of the NetThreads project: slides

  • The Case for Hardware Transactional Memory in Software Packet Processing, (pdf, ps, pdf slides, bibtex) Martin Labrecque and J. Gregory Steffan, ACM/IEEE Symposium on Architectures for Networking and Communications Systems, La Jolla, USA, October 2010.

  • Efficient Event Processing through Reconfigurable Hardware for Algorithmic Trading, (bibtex), Mohammad Sadoghi, Martin Labrecque, Harsh Singh, Warren Shum, Hans-Arno Jacobsen, International Conference on Very Large Data Bases, Singapore, September 2010.

  • Caliper: A Tool to Generate Precise and Closed-loop Traffic, (bibtex) Monia Ghobadi, Martin Labrecque, Geoffrey Salmon, Kaveh Aasaraai, Soheil Hassas Yeganeh, Yashar Ganjali, J. Gregory Steffan, SIGCOMM Conference, India, August 2010.

  • Application-Specific Signatures for Transactional Memory in Soft Processors, (pdf, ps, ppt slides, bibtex) Martin Labrecque, Mark Jeffrey and J. Gregory Steffan, 6th International Symposium on Applied Reconfigurable Computing, Bangkok, Thailand, March 2010. (best paper award)

  • Fast Critical Sections via Thread Scheduling for FPGA-based Multithreaded Processors, (pdf, ps, ppt slides, bibtex) Martin Labrecque and J. Gregory Steffan, 19th International Conference on Field Programmable Logic and Applications (FPL), (Prague, Czech Republic), September 2009.

  • NetThreads: Programming NetFPGA with Threaded Software, (pdf, ps, ppt slides, bibtex) Martin Labrecque, J. Gregory Steffan, Geoffrey Salmon, Monia Ghobadi, Yashar Ganjali, NetFPGA Developers Workshop, Palo Alto, CA, August, 2009. (2nd best presentation Award)

  • NetFPGA-based Precise Traffic Generation, (pdf, pptx slides) Geoffrey Salmon, Monia Ghobadi, Yashar Ganjali, Martin Labrecque, J. Gregory Steffan, NetFPGA Developers Workshop, Palo Alto, CA, August, 2009.

  • Scaling Soft Memory Systems, (pdf, ps, ppt slides, bibtex) Martin Labrecque, Peter Yiannacouras and J. Gregory Steffan, IEEE Symposium on Field-Programmable Custom Computing Machines, Palo Alto, CA, April, 2008.

  • Improving Pipelined Soft Processors with Multithreading, (pdf, ps, ppt slides, bibtex) Martin Labrecque and J. Gregory Steffan, 17th International Conference on Field Programmable Logic and Applications (FPL), (Amsterdam, Netherlands), August 2007.

  • Custom code generation for soft processors, (pdf, ps, ppt slides, bibtex) Martin Labrecque, Peter Yiannacouras, and J. Gregory Steffan, Special Issue: Reconfigurable and Adaptive Architecture Workshop, ACM SIGARCH Computer Architecture News, Volume 35, Issue 3 (June 2007), p. 9-19.

  • Custom code generation for soft processors, (pdf, ps, ppt slides, bibtex) Martin Labrecque, Peter Yiannacouras, and J. Gregory Steffan, Reconfigurable and Adaptive Architecture Workshop, (Orlando, FL, USA), IEEE/ACM MICRO'39, December 2006.

  • Scaling Task Graphs for Network Processors, (pdf, ps, ppt slides, bibtex) Martin Labrecque and J. Gregory Steffan, IFIP International Conference on Network and Parallel Computing, Tokyo, Japan, October, 2006.

  • M. Labrecque and G. Steffan, Scaling task graphs for network processors, in 2006 Conference for Languages, Compilers, and Tools for Embedded Systems (LCTES) Poster Abstracts, (Ottawa, Ontario, Canada), pp. 41-44, ACM SIGPLAN/SIGBED, June 14-16 2006.

  • Towards a Compilation Infrastructure for Network Processors, (pdf, bibtex) Martin Labrecque, Masters Thesis, Department of Electrical and Computer Engineering, University of Toronto, January, 2006.

Example of system using a multithreaded soft processor:

  • Automated Embedded Optical Object Recognition, (pdf) Martin Labrecque, Muttee Sheikh, Jill San Luis, Benzakhar Manashirov and Mohammed Elsayed, 1st Prize in Innovate Canada FPGA Programming Competition, 2008.

Some of my involvements at the University of Toronto:

The papers above are subject to copyright by ACM, IEEE, or other entities.


Contact:
At school, you are likely to find me in the SF2206 lab in the Sandford Fleming building. Its mailling address is:

Dept. of Electrical & Computer Engineering,
University of Toronto,
10 King's College Road,
Toronto, Ontario,
Canada, M5S 3G4

Otherwise, I'm either at my residence (on St-George St.) or at some indefinite location in space. You can also write to me at this address: martinl at eecg.utoronto.ca

http://z.about.com/d/webclipart/1/0/q/O/1/un1.gif - 3.7 K

As you might know, I am a French-Canadian so if you need help in French or want to know more about Quebec, talk to me.

Bonjour à tous mes collègues québécois! C'est toujours un plaisir de rencontrer des compatriotes partout où l'on va. N'hésitez pas a me contacter.

Interesting Startups from Toronto:

  • Pueblo Science -- developing science literacy, science camps and after-school programs in Toronto.

Links:

Locations of visitors to this page


Attorneys