Mohamed S. Abdelfattah

University of Toronto
Electrical and Computer Engineering
10 King's College Road
Toronto, ON, CANADA
M5S 3G4

Office: D. L. Pratt, Room 372 [MAP]

m o h a m e d [at] eecg.utoronto.ca




















I finished my PhD in the department of electrical and computer engineering at the University of Toronto where I researched new FPGA architectures with my advisor Vaughn Betz.


My Research: Embedded NoCs for FPGAs

By incorporating networks-on-chip (NoCs) on FPGAs, we can make FPGA designs more efficient, scalable and easier to complete.

  • In these papers [FPT'12, TRETS'13] and talk we quantified the area and speed difference between hard and soft NoC components on FPGAs and found that hard components are on average 30X smaller and 6X faster than soft.

  • After that we investigated power and energy in these [FPL'13, TVLSI'13] papers and talk and found that embedded NoCs can be surprisingly energy-efficient compared to even the simplest FPGA interconnect.

  • In this [IEEE Micro] paper we argued that embedded NoCs can be used as the ``infrastructure interconnect" for FPGA compute applications and showed that they are more efficient than custom soft buses even when the NoC is vastly underutilized.

  • In this [FPGA'15] paper we showed how to connect an embedded NoC to the FPGA fabric, and how to use the embedded NoC with FPGA design styles. Two application case studies -- JPEG compression and Ethernet switching highlighted the NoC's capability in easing timing closure, improving interconnect efficiency and switching high-bandwidth data.

  • In this [FPL'16] paper we presented a CAD system -- LYNX -- that automatically connects a user application to our embedded NoC. LYNX implements both streaming and transaction communication and creates NoC-based interconnection solutions that are generally more efficient than Qsys buses.

Check the Software tab for embedded NoC Software.

News:

  • Paper accepted to the IEEE Transactions on Computers.
  • Received the Faculty Teaching Award! [web]
  • Paper accepted to FPL'16 conference in Switzerland -- nominated for the Michel Servit best paper award!
  • Received the TA Teaching Excellence Award! [web]
  • Paper accepted to FPT 2015 conference in New Zealand.
  • "The Power of Communication" paper selected as one of the most significant papers in the last 25 years of the FPL conference! [photo]
  • Demo paper accepted at FPL'15 in London! We're presenting all our embedded NoC tools and toys there.
  • Received the ECE Teaching Assistant Award!
  • US Patent application on embedded NoCs published.
  • Paper accepted to FPGA'15 conference in Monterey, CA -- received the best paper award! [photo, press]
  • Paper accepted to TVLSI journal.
  • Completed a 5-month internship in the OpenCL team at Altera Corporation [Paper]
  • Named UTAA Graduate Scholar [press].
  • Organized distinguished lecture for Professor Adel Sedra. [video, press, press]
  • Paper accepted to IEEE Micro.
  • Received the Vanier Canada Graduate Scholarship -- the highest graduate award in Canada!
  • Paper accepted to FPL'13 conference in Portugal -- received Stamatis Vassiliadis best paper award! [press, photo]
  • Invited to submit a journal paper to TRETS.
  • Paper accepted to FPT'12 conference in Korea.

Peer-Reviewed Articles

New! Design and Applications for Embedded Networks-on-Chip on FPGAs [PDF] [LINK] [VIDEO]
Mohamed S. Abdelfattah and Vaughn Betz
IEEE Transactions on Computers (TCOMP)

New! LYNX: CAD for Embedded NoCs on FPGAs [PDF]
Mohamed S. Abdelfattah and Vaughn Betz
International Symposium on Field-Programmable Logic and Applications (FPL), August 2016, Lausanne, Switzerland.
*Nominated for the Michel Servit Best Paper Award*

Take the Highway: Design for Embedded NoCs on FPGAs[LINK] [PDF] [PPT]
Mohamed S. Abdelfattah, Andrew Bitar and Vaughn Betz
International Symposium on Field-Programmable Gate-Arrays (FPGA), February 2015, Monterey, U.S.A.
*Best Paper Award*

Bringing Programmability to the Data Plane: Packet Processing with a NoC-Enhanced FPGA [PDF]
Andrew Bitar, Mohamed S. Abdelfattah and Vaughn Betz
IEEE International Conference on Field-Programmable Technology (FPT). Dec. 2015, Queenstown, New Zealand.

Design and Simulation Tools for Embedded NoCs on FPGAs [Demo] [LINK] [PDF] [POSTER]
Mohamed S. Abdelfattah, Andrew Bitar, Ange Yaghi and Vaughn Betz
IEEE International Conference on Field-Programmable Logic and Applications (FPL). Sept. 2015, London, UK.

Power Analysis of Embedded NoCs on FPGAs and Comparison With Custom Buses[LINK] [PDF]
Mohamed S. Abdelfattah and Vaughn Betz
IEEE Transactions on Very Large Scale Integration (TVLSI), February 2015.

The Case for Embedded Networks-on-Chip on FPGAs [LINK] [PDF]
Mohamed S. Abdelfattah and Vaughn Betz
IEEE Micro Magazine, February 2014.

Gzip on a Chip: High Performance Lossless Data Compression on FPGAs using OpenCL [LINK] [PDF]
Mohamed S. Abdelfattah, Andrei Hagiescu and Deshanand Singh
ACM International Conference Proceedings of IWOCL, Dec 2014.

OpenCL Implementation of Gzip on Field-Programmable Gate-Arrays [LINK] [PPT]
Mohamed S. Abdelfattah, Andrei Hagiescu and Deshanand Singh
International Workshop on OpenCL (IWOCL), May 2014.

Networks-on-Chip for FPGAs: Hard, Soft or Mixed? [LINK] [PDF]
Mohamed S. Abdelfattah and Vaughn Betz
ACM Transactions on Reconfigurable Technology and Systems (TRETS), August 2014.

The Power of Communication: Energy-Efficient NoCs for FPGAs [LINK] [PPT] [PDF]
Mohamed S. Abdelfattah and Vaughn Betz
IEEE International Conference on Field-Programmable Logic and Applications (FPL). Sept. 2013, Porto, Portugal.
*S. Vassiliadis Best Paper Award*
*Selected as one of most significant papers in 25 years of FPL conference history*

Design Tradeoffs for Hard and Soft FPGA-based Networks-on-Chip [LINK] [PPT] [PDF]
Mohamed S. Abdelfattah and Vaughn Betz
IEEE International Conference on Field-Programmable Technology (FPT). Dec. 2012, Seoul, Korea.

Augmenting FPGAs with Embedded Networks-on-Chip [PPT] [PDF]
Mohamed S. Abdelfattah and Vaughn Betz
Workshop on the Intersections of Computer Architecture and Reconfigurable Logic (CARL). Dec. 2013, Davis, U.S.A.

Transparent Structural Online Test for Reconfigurable Systems [LINK] [PDF]
Mohamed S. Abdelfattah, L. Bauer, C. Braun, M. E. Imhof, M. A. Kochte, Joerg Henkel and Hans-Joachim Wunderlich
IEEE International On-Line Testing Symposium (IOLTS). June 2012, Sitges, Spain.

2.2 GHz LC VCO for RFID on a 0.5-um digital gate-array designed for ultra-thin silicon substrates [LINK] [PDF]
Mohamed S. Abdelfattah, D. Ferenci, M. Groezing, M. Berroth, C. Scherjon and Joachim N. Burghartz
German Microwave Conference (GeMiC). March 2011, Darmstadt, Germany.

Design of a RF Transmitter for RFID Tags with Ultra Thin Silicon Substrates [POSTER] [PDF]
Mohamed S. Abdelfattah, D. Ferenci, M. Groezing, M. Berroth, C. Scherjon and Joachim N. Burghartz
Workshop on Circuit Design and Digital Signal Processing (ProRISC). Nov. 2009, Veldhoven, The Netherlands.

Recorded Talks

Dissertations

Embedded Networks-on-Chip for Field-Programmable Gate-Arrays [PDF]
PhD thesis, University of Toronto, August 2016.
Advisor: Vaughn Betz

Evaluation of Advanced Techniques for Structural FPGA Self-Test [PDF]
Master's thesis, University of Stuttgart, August 2011.
Advisor: Hans-Joachim Wunderlich

Design of an RF Transmitter for RFID Tags in a New Technology with Ultra-Thin Silicon Substrates [PDF]
Bachelor's thesis, German University in Cairo, August 2009.
Advisor: Manfred Berroth

Patents

Field-Programmable Gate-Array with Embedded Network-on-Chip Hardware and Design Flow [PDF]
Mohamed S. Abdelfattah and Vaughn Betz
US Patent Application

An online tool to prototype hard, soft or mixed NoCs on FPGAs.
It provides a visual front-end for some of the data that we have gathered
in our research; area, frequency and power measurements from synthesized
router implementations.

We aim to provide our data for fellow researchers to either use in
their own work, or to see the backing data for our research papers.



NoC simulator with hooks for co-simulating RTL designs in Verilog.
This tools allow you to easy configure Booksim to model any NoC,
then use that NoC in your RTL (e.g. Verilog) design exactly like
it is a hardware component.




LYNX automatically interconnects FPGA applications using an NoC.
Its input is an application connectivity graph, and it maps the
application onto an NoC and generates simulation and synthesis files.

























For more cool software and benchmarks, check out Vaughn Betz' downloads page.

Mentoring

  • [Summer 2015] I worked with ECE undergraduate students Harshita Huria and Aya ElSayed on creating video processing hardware modules using high-level synthesis.
  • [Summer 2013] I worked with ECE undergraduate student Ange Yaghi (Summer 2013) who developed NoC Designer and implemented/verified HDL networks-on-chip.

Teaching Assistantships

  • ECE297 Communication and Design (Winter 2015, 2016)
    Head Teaching Assistant and helped course redesign.
    Instructor: Vaughn Betz

  • ECE241 Digital Systems (Fall 2012, 2013, 2015)
    Instructor: Jason Anderson

  • ECE243 Computer Organization (Winter 2012, 2013)
    Instructor: Andreas Moshovos
For office hours please consult my calendar for a free slot then drop by my office or send me an email.

CV [PDF]


View Mohamed's Citations on Google Scholar

View Mohamed's Profile on LinkedIn

Education History

  • Ph.D. at the University of Toronto, supervised by Vaughn Betz: 2011 - present
  • M.Sc. at the University of Stuttgart, supervised by Hans-Joachim Wunderlich: 2009 - 2011
  • B.Sc. at the German University in Cairo, thesis supervised by Manfred Berroth: 2005 - 2009

Thanks to Franzi Roesner for the webpage template.
Some links: DLS - FPGA Seminar - EECG - TCFPGA - IEEE - ACM - Wiki - NoC Designer

Last updated September 2017.