Mohamed S. Abdelfattah

I am a second year PhD student in the department of electrical and computer engineering at the University of Toronto where I am researching new FPGA architectures with my advisor Vaughn Betz.

About My Research

Field-programmable gate-arrays (FPGAs) have the flexibility of implementing any logic function, more importantly, they are increasingly becoming a platform for interconnecting small memories, digital signal processing functions and even complete processor cores.

My research aims to strengthen FPGAs' ability to interconnect different compute elements. I am exploring the possibility of upgrading the FPGA interconnect to include a packet-switched network-on-chip (NoC). By pairing that with latency-insensitive design style, it can overcome scalability bottlenecks (interconnect slower than logic), simplify design (ease timing closure), and open the door to exciting new applications (e.g. parallel compilation, partial reconfiguration and multi-chip interconnect).

I started by looking at how to "build" the NoC. Our recent study shows that implementing a NoC from hard/embedded routers and soft/programmable links makes it 22X more area efficient and 4X faster than a completely soft NoC while maintaining the freedom of implementing any interconnection topology. This means that a 64-node NoC built this way occupies 0.6% chip area of a large FPGA compared to 12% for a soft NoC.

Conference Proceedings

• Mohamed S. Abdelfattah and Vaughn Betz "Design Tradeoffs for Hard and Soft FPGA-based Networks-on-Chip," IEEE International Conference on Field-Programmable Technology (FPT), pp.95-103, Dec. 2012 [PDF] [PPT]


• Mohamed S. Abdelfattah, Lars Bauer, Claus Braun, Michael E. Imhof, Michael A. Kochte, Hongyan Zhang, Joerg Henkel and Hans-Joachim Wunderlich "Transparent Structural Online Test for Reconfigurable Systems," IEEE International On-Line Testing Symposium (IOLTS), pp.37-42, June 2012 [LINK] [PDF]


• M.S. Abdelfattah, D. Ferenci, M. Groezing, M. Berroth, C. Scherjon and J.N. Burghartz, "2.2 GHz LC VCO for RFID on a 0.5-um digital gate-array designed for ultra-thin silicon substrates" German Microwave Conference (GeMiC), pp.1-4, March 2011 [LINK] [PDF]


• M.S. Abdelfattah, D. Ferenci, M. Groezing, M. Berroth, C. Scherjon and J.N. Burghartz "Design of a RF Transmitter for RFID Tags in a New Technology with Ultra Thin Silicon Substrates" in Circuit Design and digital Signal Processing, conference proceedings of ProRISC, pp.193-196, Nov. 2009 [PDF] [POSTER]

Dissertations

• Master's Thesis: Evaluation of Advanced Techniques for Structural FPGA Self-Test, August 2011 [PDF]


• Bachelor's Thesis Design of an RF Transmitter for RFID Tags in a New Technology with Ultra-Thin Silicon Substrates, August 2009 [PDF]

Teaching Assistantships

• ECE241 Digital Systems (Fall 2012)
  Instructor: Jason Anderson
  
  
• ECE243 Computer Organization (Winter 2012, 2013)
  Instructor: Andreas Moshovos

CV [PDF]

Education History

• Ph.D. at the University of Toronto, supervised by Vaughn Betz: 2011 - present
• M.Sc. at the University of Stuttgart, supervised by Hans-Joachim Wunderlich: 2009 - 2011
• B.Sc. at the German University in Cairo, thesis supervised by Manfred Berroth: 2005 - 2009