Farid N. Najm received the B.E. degree (with distinction) in Electrical Engineering from the American University of Beirut (AUB) in 1983, and the M.S. and Ph.D. degrees in Electrical and Computer Engineering from the University of Illinois at Urbana-Champaign (UIUC) in 1986 and 1989, respectively. He worked with Texas Instruments in Dallas, Texas, 1989-1992, then joined the ECE Department at UIUC as an Assistant Professor, becoming Associate Professor in 1997. In 1999, he joined the ECE Department at the University of Toronto, where he is now Professor and Chair. Dr. Najm's research interests are in the general area of computer-aided design (CAD) for integrated circuits, with an emphasis on circuit level issues related to power dissipation, timing, and reliability. Dr. Najm is a Fellow of the Canadian Academy of Engineering (CAE) and a Fellow of the IEEE.
My general research area is Computer-Aided Design (CAD) for Integrated Circuits. There is a continuous need to develop new CAD tools and design methodologies in order to keep up with the advances in Integrated Circuits (IC) technology and with the performance goals that are set for ICs. The International Technology Roadmap for Semiconductors ( ITRS), also available from SEMATECH and sponsored by the Semiconductor Industry Association (SIA) among others, provides a forecast of the future of integrated circuits technology. Future integrated circuits, at the nanometer scale and beyond, will allow the integration of whole electronic systems on a single IC, leading to so-called system-on-a-chip (SOC) designs.
IC design is difficult, costly, and time consuming. It is not uncommon for the design of a large microprocessor chip to take 3 years, to require a team of about a 1000 designers, and to cost several hundred million dollars (US). As new generations of semiconductor technology become available, new problems arise in IC design, which require a next generation of CAD tools and methodologies. More information on the need for advances in design technology can be obtained from the National Science Foundation (NSF), the Semiconductor Industry Association (SIA), the Microelectronics Advanced Research Corporation (MARCO), and from the Semiconductor Research Corporation (SRC).
In this framework, my work is focused on managing the design problems related to power dissipation and circuit timing. I have worked on issues related to average power (thermal concerns, battery life), transient power (grid noise, metal reliability), as well as leakage current. Currently, my work is focused on power grid verification and optimization and on managing the impact of process and environmental variability on circuit timing and chip leakage.Over the years, my research has been supported by grants and contracts from a variety of sources. Specifically, I would like to acknowledge the generous support of the University of Illinois, the National Science Foundation (NSF), Intel Corporation, Rockwell Corporation, Digital Equipment Corporation (DEC), the Semiconductor Research Corporation (SRC), Texas Instruments Inc., IBM Corporation, the Natural Sciences and Engineering Research Council of Canada (NSERC), the University of Toronto, Nortel Networks, Micronet, ATI Technologies, Altera Corporation, Canada Foundation for Innovation, and Advanced Micro Devices (AMD), Inc.