Bibliography

[Return to my homepage]

[1]

C. Ababei and K. Bazargan. Placement method targeting predictability robustness and performance. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 81-85, San Jose, CA, November 9-13 2003.

[2]

W. Abadeer and W. Ellis. Behavior of NBTI under AC dynamic circuit conditions. In International Reliability Physics Symposium (IRPS), pages 17-22, Dallas, TX, March 30-April 4 2003.

[3]

S. Abbaspour, M. Pedram, A. Ajami, and C. Kashyap. Fast interconnect and gate timing analysis for performance optimization. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14(12):1383-1388, December 2006.

[4]

S. Abbaspour, R. Banerji, P. Feldmann, and D. D. Ling. Efficient variational interconnect modeling for statistical timing analysis by combined sensitivity analysis and model-order reduction. In ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU-07), pages 86-91, Austin, Texas, February 26-27 2007.

[5]

S. Abbaspour, H. Fatemi, and M. Pedram. Parametrized non-gaussian variational gate timing analysis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 26(8):1495-1508, August 2007.

[6]

A. Abdollahi, F. Fallah, and M. Pedram. Runtime mechanisms for leakage current reduction in CMOS VLSI circuits. In ACM/IEEE International Symposium on Low Power Electronics and Design, pages 213-218, Monterey, California, August 12-14 2002.

[7]

A. Abdollahi, F. Fallah, and M. Pedram. Leakage current reduction in sequential circuits by modifying the scan chains. In IEEE International Symposium on Quality Electronic Design (ISQED), pages 49-54, San Jose, CA, March 24-26 2003.

[8]

A. Abdollahi, F. Fallah, and M. Pedram. Leakage current reduction in CMOS VLSI circuits by input vector control. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12(2):140-154, February 2004.

[9]

A. Abdollahi, F. Fallah, and M. Pedram. An effective power mode transition technique in MTCMOS circuits. In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages 37-42, Anaheim, CA, June 13-17 2005.

[10]

A. Abdollahi and M. Pedram. A new canonical form for fast boolean matching in logic synthesis and verification. In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages 379-384, Anaheim, CA, June 13-17 2005.

[11]

A. Abdollahi. Probabilistic decision diagrams for exact probabilistic analysis. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 266-272, San Jose, CA, November 5-8 2007.

[12]

A. I. Abou-Seido, B. Nowak, and C. Chu. Fitted elmore delay: a simple and accurate interconnect delay model. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12(7):691-696, July 2004.

[13]

J. A. Abraham and W. K. Fuchs. Fault and error models for VLSI. In Proceedings of the IEEE, pages 639-654, May 1986. Published as Proceedings of the IEEE, volume 74, number 5.

[14]

J. A. Abraham and H-C. Shih. Testing of MOS VLSI circuits. In International Symposium on Circuits and Systems, Kyoto, Japan, June 5-7 1985.

[15]

J. Abraham. Power calculation and modeling in deep submicron. In ACM/IEEE International Symposium on Low Power Electronics and Design, pages 124-126, Monterey, CA, August 10-12 1998.

[16]

Y. Abulafia and A. Kornfeld. Estimation of FMAX and ISB in microprocessors. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 13(10):1205-1209, October 2005.

[17]

E. Acar, S. Nassif, Y. Liu, and L. T. Pileggi. Assessment of true worst case circuit performance under interconnect parameter variations. In IEEE International Symposium on Quality Electronic Design (ISQED), pages 431-436, San Jose, CA, March 26-28 2001.

[18]

E. Acar, F. Dartu, and L. Pileggi. TETA: Transistor-level waveform evaluation for timing analysis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 21(5):605-616, May 2002.

[19]

E. Acar, S. Nassif, Y. Liu, and L. T. Pileggi. Time-domain simulation of variational interconnect models. In IEEE International Symposium on Quality Electronic Design (ISQED), pages 419-424, San Jose, CA, March 18-21 2002.

[20]

E. Acar, A. Devgan, R. Rao, F. Liu, H. Su, S. Nassif, and J. Burns. Leakage and leakage sensitivity computation for combinational circuits. In ACM/IEEE International Symposium on Low Power Electronics and Design, pages 96-99, Seoul, Korea, August 25-27 2003.

[21]

G. Acciani, D. Congedo, and B. Dilecce. Improving the computational efficiency of the tree relaxation method for an iterative solution of linear circuit equations. IEEE Transactions on Computer-Aided Design, 10(5):668-670, May 1991.

[22]

B. D. Ackland and R. A. Clark. Event-EMU : an event driven timing simulator for MOS VLSI circuits. In IEEE International Conference on Computer-Aided Design, pages 80-83, 1989.

[23]

B. Ackland and C. Nicol. High performance dsps - what's hot and what's not? In ACM/IEEE International Symposium on Low Power Electronics and Design, pages 1-6, Monterey, CA, August 10-12 1998.

[24]

D. Adler. SIMMOS: a multiple-delay switch-level simulator. In 23rd ACM/IEEE Design Automation Conference, pages 159-163, Las Vegas, NV, June 29 - July 2 1986.

[25]

D. Adler. A dynamically-directed switch model for MOS logic simulation. In 25th ACM/IEEE Design Automation Conference, pages 506-511, Anaheim, CA, June 12-15 1988.

[26]

D. Adler. Switch-level simulation using dynamic graph algorithms. IEEE Transactions on Computer-Aided Design, 10(3):346-355, March 1991.

[27]

A. Agarwal, D. Blaauw, and V. Zolotov. Statistical clock skew analysis considering intra-die process variations. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 914-921, San Jose, CA, November 9-13 2003.

[28]

A. Agarwal, D. Blaauw, and V. Zolotov. Statistical timing analysis for intra-die process variations with spatial correlations. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 900-907, San Jose, CA, November 9-13 2003.

[29]

A. Agarwal, D. Blaauw, V. Zolotov, and S. Vrudhula. Computation and refinement of statistical bounds on circuit delay. In ACM/IEEE 40th Design Automation Conference (DAC-03), pages 348-353, Anaheim, CA, June 2-6 2003.

[30]

A. Agarwal, V. Zolotov, and D. T. Blaauw. Statistical timing analysis using bounds and selective enumeration. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 22(9):1243-1260, September 2003.

[31]

K. Agarwal, D. Sylvester, and D. Blaauw. An effective capacitance based driver output model for on-chip RLC interconnects. In ACM/IEEE 40th Design Automation Conference (DAC-03), pages 376-381, Anaheim, CA, June 2-6 2003.

[32]

K. Agarwal, D. Sylvester, and D. Blaauw. Simple metrics for slew rate of RC circuits based on two circuit moments. In ACM/IEEE 40th Design Automation Conference (DAC-03), pages 950-953, Anaheim, CA, June 2-6 2003.

[33]

A. Agarwal, F. Dartu, and D. Blaauw. Statistical gate delay model considering multiple input switching. In ACM/IEEE 41st Design Automation Conference (DAC-04), pages 658-663, San Diego, CA, June 7-11 2004.

[34]

A. Agarwal, C.-H. Kim, S. Mukhopadhyay, and K. Roy. Leakage in nano-scale technologies: mechanisms, impact and design considerations. In ACM/IEEE 41st Design Automation Conference (DAC-04), pages 6-11, San Diego, CA, June 7-11 2004.

[35]

A. Agarwal, V. Zolotov, and D. T. Blaauw. Statistical clock skew analysis considering intradie-process variations. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 23(8):1231-1242, August 2004.

[36]

K. Agarwal, D. Sylvester, and D. Blaauw. A library compatible driver output model for on-chip RLC transmission lines. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 23(1):128-136, January 2004.

[37]

K. Agarwal, D. Sylvester, and D. Blaauw. A simple metric for slew rate of RC circuits based on two circuit moments. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 23(9):1346-1354, September 2004.

[38]

K. Agarwal, D. Sylvester, D. Blaauw, F. Liu, S. Nassif, and S. Vrudhula. Variational delay metrics for interconnect timing analysis. In ACM/IEEE 41st Design Automation Conference (DAC-04), pages 381-384, San Diego, CA, June 7-11 2004.

[39]

A. Agarwal, K. Chopra, D. Blaauw, and V. Zolotov. Circuit optimization using statistical static timing analysis. In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages 321-324, Anaheim, CA, June 13-17 2005.

[40]

A. Agarwal, K. Kang, S. K. Bhunia, J. D. Gallagher, and K. Roy. Effectiveness of low power dual-vt designs in nano-scale technologies under process parameter variations. In ACM/IEEE International Symposium on Low Power Electronics and Design, pages 14-19, San Diego, CA, August 8-10 2005.

[41]

A. Agarwal, K. Kang, and K. Roy. Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variations. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD-05), pages 736-741, San Jose, CA, November 6-10 2005.

[42]

K. Agarwal, M. Agarwal, D. Sylvester, and D. Blaauw. Statistical interconnect metrics for physical-design optimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25(7):1273-1288, July 2006.

[43]

K. Agarwal, D. Sylvester, and D. Blaauw. Modeling and analysis of crosstalk noise in coupled RLC interconnects. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25(5):892-901, May 2006.

[44]

K. Agarwal, R. Rao, D. Sylvester, and R. Brown. Parametric yield analysis and optimization in leakage dominated technologies. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 15(6):613-623, June 2007.

[45]

M. Agarwal, B. C. Paul, M. Zhang, and S. Mitra. Circuit failure prediction and its application to transistor aging. In ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU-07), pages 98-105, Austin, Texas, February 26-27 2007.

[46]

M. Agarwal, V. Balakrishnan, A. Bhuyan, K. Kim, M. Mizuno, B. C. Paul, W. Wang, Y. Cao, and S. Mitra. Optimized circuit failure prediction for aging: practicality and promise. In ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU-08), pages 116-119, Monterey, CA, February 25-26 2008.

[47]

A. Agarwal and M. Levy. The KILL rule for multicore. In ACM/IEEE 44th Design Automation Conference (DAC-07), pages 750-753, San Diego, CA, June 4-8 2007.

[48]

K. Agarwal and F. Liu. Efficient computation of current flow in signal wires for reliability analysis. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 741-746, San Jose, CA, November 5-8 2007.

[49]

K. Agarwal and S. Nassif. Statistical analysis of SRAM cell stability. In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages 57-62, San Francisco, CA, July 24-28 2006.

[50]

K. Agarwal and S. Nassif. Characterizing process variation in nanometer CMOS. In ACM/IEEE 44th Design Automation Conference (DAC-07), pages 396-399, San Diego, CA, June 4-8 2007.

[51]

K. Agarwal and S. Nassif. The impact of random device variation on SRAM cell stability in sub-90nm CMOS technologies. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 16(1):86-97, January 2008.

[52]

A. Agarwal and K. Roy. A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime. In ACM/IEEE International Symposium on Low Power Electronics and Design, pages 18-21, Seoul, Korea, August 25-27 2003.

[53]

A. Agarwal and R. Vermuri. Hierarchical performance macromodels of feasible regions for synthesis of analog and RF circuits. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD-05), pages 430-436, San Jose, CA, November 6-10 2005.

[54]

B. N. Agarwala, M. J. Attardo, and P. Ingraham. Dependence of electromigration-induced failure time on length and width of aluminum thin-film conductors. Journal of Applied Physics, 41(10):3954-3960, September 1970.

[55]

R. Aggrawal, R. Murgai, and M. Fujita. Speeding up technology-independent timing optimization by network partitioning. In IEEE/ACM International Conference on Computer-Aided Design, pages 83-90, San Jose, CA, November 9-13 1997.

[56]

Y. Aghaghiri, F. Fallah, and M. Pedram. Irredundant address bus encoding for low power. In ACM/IEEE International Symposium on Low Power Electronics and Design, pages 182-187, Huntington Beach, California, August 6-7 2001.

[57]

Y. Aghaghiri, F. Fallah, and M. Pedram. ALBORZ: address level bus power optimization. In IEEE International Symposium on Quality Electronic Design (ISQED), pages 470-475, San Jose, CA, March 18-21 2002.

[58]

Y. Aghaghiri, F. Fallah, and M. Pedram. Reducing transitions on memory buses using sector-based encoding technique. In ACM/IEEE International Symposium on Low Power Electronics and Design, pages 190-195, Monterey, California, August 12-14 2002.

[59]

Y. Aghaghiri, F. Fallah, and M. Pedram. Transition reduction in memory buses using sector-based encoding techniques. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 23(8):1164-1174, August 2004.

[60]

A. Agnihotri, M. C. Yildiz, A. Khatkhate, A. Mathur, S. Ono, and P. H. Madden. Fractional cut: improved recursive bisection placement. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 307-310, San Jose, CA, November 9-13 2003.

[61]

V. D. Agrawal, K-T Cheng, and P. Agrawal. CONTEST: a concurrent test generator for sequential circuits. In 25th ACM/IEEE Design Automation Conference, pages 84-89, Anaheim, CA, June 12-15 1988.

[62]

V. D. Agrawal, K-T. Cheng, and P. Agrawal. A directed search method for test generation using a concurrent simulator. IEEE Transactions on Computer-Aided Design, 8(2):131-138, February 1989.

[63]

A. Agrawal, H. Li, and K. Roy. DRG-cache: A data retention gated-ground cache for low power. In ACM/IEEE 39th Design Automation Conference (DAC-02), pages 473-478, New Orleans, LA, June 10-14 2002.

[64]

P. Agrawal and S. M. Reddy. Test generation at MOS level. In IEEE International Conference on Computers, Systems, and Signal Processing, pages 1116-1119, Bangalore, India, Dec. 10-12 1984.

[65]

V. D. Agrawal and S. C. Seth. Probabilistic testability. In IEEE International Conference on Computer Design: VLSI in Computers, pages 562-565, Port Chester, NY, Oct. 7-10 1985.

[66]

V. D. Agrawal. Information theory in digital testing - a new approach to functional test pattern generation. In IEEE International Conference on Circuits and Computers, pages 928-931, Port Chester, NY, Oct. 1-3 1980.

[67]

V. D. Agrawal. An information theoretic approach to digital fault testing. IEEE Transactions on Computers, C-30(8):582-587, August 1981.

[68]

P. Agrawal. Test generation at switch-level. In IEEE International Conference on Computer-Aided Design, pages 128-130, Santa Clara, CA, Nov. 12-15 1984.

[69]

R. Ahmadi and F. N. Najm. Timing analysis in presence of power supply and ground voltage variations. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 176-183, San Jose, CA, November 9-13 2003.

[70]

E. Ahmed and J. Rose. The effect of LUT and cluster size on deep-submicron FPGA performance and density. IEEE Transactions on Very Large Scale Intergration (VLSI) Systems, 12(3):288-298, March 2004.

[71]

R. Aitken and S. Becker. Cell library techniques using advanced transistor structures. In International Conference on Integrated Circuit Design and Technology (ICICDT), pages 199-204, Austin, TX, May 17-20 2004.

[72]

A. A. Ajami, K. Banerjee, and M. Pedram. Analysis of substrate thermal gradient effects on optimal buffer insertion. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 44-48, San Jose, CA, November 4-8 2001.

[73]

A. H. Ajami, K. Banerjee, M. Pedram, and L. P.P.P. van Ginneken. Analysis of non-uniform temperature-dependent interconnect performance in high performance ics. In ACM/IEEE 38th Design Automation Conference (DAC-01), pages 567-572, Las Vegas, NV, June 18-22 2001.

[74]

A. H. Ajami, K. Banerjee, and M. Pedram. Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(6):849-861, June 2005.

[75]

S. B. Akers, Jr. On a theory of boolean functions. SIAM Journal, 7(4):487-498, December 1959.

[76]

S. B. Akers. Functional testing with binary decision diagrams. In IEEE 8th International Conference on Fault-Tolerant Computing, pages 75-82, Tolouse, France, June 21-23 1978.

[77]

S. A. Al-Arian and D. P. Agrawal. Physical failures and fault models of CMOS circuits. IEEE Transactions on Circuits and Systems, CAS-34(3):269-279, March 1987.

[78]

A. A. Al-Yamani, S. Ramsundar, and D. K. Pradhan. A defect tolerance scheme for nanotechnology circuits. IEEE Transactions on Circuits and Systems, 54(11):2402-2409, November 2007.

[79]

M. M. Alaybeyi, J. Y. Lee, and R. A. Rohrer. Numerical integration algorithms and asymptotic waveform evaluation (AWE). In IEEE/ACM International Conference on Computer-Aided Design, pages 76-79, Santa Clara, CA, November 8-12 1992.

[80]

C. Albrecht, B. Korte, J. Schietke, and J. Vygen. Cycle time and slack optimization for VLSI chips. In IEEE/ACM International Conference on Computer-Aided Design, pages 232-238, San Jose, CA, November 7-11 1999.

[81]

E. F. M. Albuquerque and M. M. Silva. A comparison by simulation and by measurement of the substrate noise generated by CMOS, CSL, and CBL digital circuits. IEEE Transactions on Circuits and Systems, 52(4):734-741, April 2005.

[82]

M. F. Ali, A. Veneris, S. Safarpour, R. Drechsler, A. Smith, and M. Abadir. Debugging sequential circuits using boolean satisfiability. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 204-209, San Jose, CA, November 7-11 2004.

[83]

M. Alidina, J. Monteiro, S. Devadas, A. Ghosh, and M. Papaefthymiou. Precomputation-based sequential logic optimization for low power. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2(4):426-436, December 1994.

[84]

M. Alidina, J. Monteiro, S. Devadas, A. Ghosh, and M. Papaefthymiou. Precomputation-based sequential logic optimization for low power. In IEEE/ACM International Conference on Computer-Aided Design, pages 74-81, San Jose, CA, November 6-10 1994.

[85]

M. Alidina, J. Monteiro, A. Ghosh, and M. Papaefthymiou. Precomputation-based sequential logic optimization for low power. In ACM/IEEE 1994 International Workshop on Low Power Design, pages 57-62, Napa, CA, April 24-27 1994.

[86]

A. Alimohammad, S. F. Fard, B. F. Cockburn, and C. Schlegel. A compact and accurate gaussian variate generator. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 16(5):517-527, May 2008.

[87]

M. Alioto, G. Palumbo, and M. Poli. Evaluation of energy consumption in RC ladder circuits driven by a ramp input. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12(10):1094-1107, October 2004.

[88]

M. Alioto, G. Palumbo, and M. Poli. Energy consumption in RC tree circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14(5):452-461, May 2006.

[89]

M. Alioto and G. Palumbo. Power estimation in adiabatic circuits: a simple and accurate model. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 9(5):608-615, October 2001.

[90]

M. Alioto and G. Palumbo. NAND/NOR adiabatic gates: power consumption evaluation and comparion versus the fan-in. IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and Applications, 49(9):1253-1262, September 2002.

[91]

M. Alioto and G. Palumbo. Design strategies for source coupled logic gates. IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and Applications, 50(5):640-654, May 2003.

[92]

M. Alioto and G. Palumbo. Impact of supply voltage variations on full adder delay: analysis and comparison. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14(12):1322-1335, December 2006.

[93]

G. A. Allan. Yield prediction by sampling IC layout. IEEE Transactions on Computer-Aided Design, 19(3):359-371, March 2000.

[94]

D. Allen, D. Behrends, and B. Stanisic. Converting a 64b powerpc processor from CMOS bulk to SOI technology. In Design Automation Conference, pages 892-897, New Orleans, LA, June 21-25 1999.

[95]

F. A. Aloul, A. Ramani, I. L. Markov, and K. A. Sakallah. Generic ILP versus specialized 0-1 ILP: An update. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 450-457, San Jose, CA, November 10-14 2002.

[96]

F. A. Aloul, B. D. Sierawski, and K. A. Sakallah. Satometer: how much have we searched. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 22(8):995-1004, August 2003.

[97]

C. J. Alpert, A. Devgan, and S. T. Quay. Buffer insertion for noise and delay optimization. In IEEE/ACM 35th Design Automation Conference, pages 362-367, San Francisco, CA, June 15-19 1998.

[98]

C. J. Alpert, A. Devgan, and S. T. Quay. Is wire tapering worthwhile? In IEEE/ACM International Conference on Computer-Aided Design, pages 430-435, San Jose, CA, November 7-11 1999.

[99]

C. J. Alpert, A. Devgan, and C. Kashyap. A two moment RC delay metric for performance optimization. In International Symposium on Physical Design, pages 69-74, San Diego, CA, April 9-12 2000.

[100]

C. J. Alpert, A. Devgan, and C. V. Kashyap. RC delay metrics for performance optimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 20(5):571-582, May 2001.

[101]

C. J. Alpert, F. Liu, C. Kashyap, and A. Devgan. Delay and slew metrics using the lognormal distribution. In ACM/IEEE 40th Design Automation Conference (DAC-03), pages 382-385, Anaheim, CA, June 2-6 2003.

[102]

C. J. Alpert, F.-Y. Liu, C. V. Kashyap, and A. Devgan. Closed-form delay and slew metrics made easy. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 23(12):1661-1669, December 2004.

[103]

C. J. Alpert. The ispd98 circuit benchmark suite. In ACM/IEEE International Symposium on Physical Design, pages 80-85, Monterey, CA, April 6-8 1998.

[104]

M. D. Altman, J. P. Bardhan, B. Tidor, and J. K. White. FFTSVD: a fast multiscale boundary-element method solver suitable for bio-MEMS and biomolecule simulation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25(2):274-284, February 2006.

[105]

A. Alvandpour, P. Larsson-Edefors, and C. Svensson. Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits. In ACM/IEEE International Symposium on Low Power Electronics and Design, pages 245-249, Monterey, CA, August 10-12 1998.

[106]

H. Amanthan, C.-H. Kim, and K. Roy. Larger-than-vdd forward body bias in sub-0.5v nanoscale CMOS. In ACM/IEEE International Symposium on Low Power Electronics and Design, pages 8-13, Newport Beach, CA, August 9-11 2004.

[107]

S. V. Amari and R. B. Misra. Closed-form expressions for distribution of sum of exponential random variables. IEEE Transactions on Reliability, 46(4):519-522, December 1997.

[108]

B. Amelifard, F. Fallah, and M. Pedram. Low-power fanout optimization using multiple threshold voltage inverters. In ACM/IEEE International Symposium on Low Power Electronics and Design, pages 95-98, San Diego, CA, August 8-10 2005.

[109]

B. Amelifard, F. Fallah, and M. Pedarm. Low-power fanout optimization using MTCMOS and multi-vt techniques. In ACM/IEEE International Symposium on Low Power Electronics and Design, pages 334-337, Tegernsee, Germany, October 4-6 2006.

[110]

B. Amelifard and M. Pedram. Design of an efficient power delivery network in an soc to enable dynamic power management. In ACM/IEEE International Symposium on Low Power Electronics and Design, pages 328-333, Portland, Oregon, August 27-29 2007.

[111]

B. Amelifard and M. Pedram. Optimal selection of voltage regulator modules in a power delivery network. In ACM/IEEE 44th Design Automation Conference (DAC-07), pages 168-173, San Diego, CA, June 4-8 2007.

[112]

B. W. Amick, C. R. Gauthier, and D. Liu. Macro-modeling concepts for the chip electrical interface. In ACM/IEEE 39th Design Automation Conference (DAC-02), pages 391-394, New Orleans, LA, June 10-14 2002.

[113]

C. S. Amin, M. H. Chowdhury, and Y. I. Ismail. Realizable RLCK circuit crunching. In ACM/IEEE 40th Design Automation Conference (DAC-03), pages 226-231, Anaheim, CA, June 2-6 2003.

[114]

C. S. Amin, F. Dartu, and Y. I. Ismail. Weibull based analytical waveform model. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 161-168, San Jose, CA, November 9-13 2003.

[115]

C. S. Amin, F. Dartu, and Y. I. Ismail. Modeling unbuffered latches for timing analysis. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 254-260, San Jose, CA, November 7-11 2004.

[116]

C. S. Amin, M. H. Chowdhury, and Y. I. Ismail. Realizable reduction of interconnect circuits including self and mutual inductances. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(2):271-277, February 2005.

[117]

C. S. Amin, F. Dartu, and Y. I. Ismail. Weibull-based analytical waveform model. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(8):1156-1168, August 2005.

[118]

C. S. Amin, Y. I. Ismail, and F. Dartu. Piece-wise approximations of RLCK circuit responses using moment matching. In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages 927-932, Anaheim, CA, June 13-17 2005.

[119]

C. S. Amin, N. Menezes, K. Killpack, F. Dartu, U. Choudhury, N. Hakim, and Y. I. Ismail. Statistical static timing analysis: how simple can we get? In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages 652-657, Anaheim, CA, June 13-17 2005.

[120]

C. Amin, C. Kashyap, N. Menezes, K. Killpack, and E. Chiprout. A multi-port current source model for multiple-input switching effects in CMOS library cells. In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages 247-252, San Francisco, CA, July 24-28 2006.

[121]

A. Amirabadi, A. Afzali-Kusha, Y. Mortazavi, and M. Nourani. Clock delayed domino logic with efficient variable threshold voltage keeper. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 15(2):125-134, February 2007.

[122]

B. S. Amrutur and M. A. Horowitz. Speed and power scaling of SRAM's. IEEE Transactions on Solid-State Circuits, 35(2):175-185, February 2000.

[123]

M. E. Amyeen, W. K. Fuchs, I. Pomeranz, and V. Boppana. Fault equivalence identification in combinational circuits using implication and evaluation techniques. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 22(7):922-936, July 2003.

[124]

H. Ananthan and K. Roy. Technology-circuit co-design in width-quantized quasi-planar double-gate SRAM. In IEEE 2005 International Conference on Integrated Circuit Design and Technology (ICICDT), pages 155-160, Austin, TX, May 9 - 11 2005.

[125]

H. Ananthan and K. Roy. A fully physical model for leakage distribution under process variations in nanoscale double-gate CMOS. In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages 413-418, San Francisco, CA, July 24-28 2006.

[126]

D. F. Anastasakis, N. Gopal, and L. T. Pillage. On the stability of moment-matching approximations in asumptotic waveform evaluation. SRC Technical Report C91905, Journal Preprint, December 1991.

[127]

D. F. Anastasakis, N. Gopal, S. Y. Kim, and L. T. Pillage. On the stability of moment-matching approximations in assymptotic waveform evaluation. In 29th ACM/IEEE Design Automation Conference, pages 207-212, Anaheim, CA, June 8-12 1992.

[128]

J. H. Anderson, F. N. Najm, and T. Tuan. Active leakage power optimization for fpgas. In ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 33-41, Monterey, CA, February 22-24 2004.

[129]

J. H. Anderson and F. N. Najm. Power-aware technology mapping for LUT-based fpgas. In IEEE International Conference on Field-Programmable Technology, pages 211-218, Hong Kong, December 16-18 2002.

[130]

J. H. Anderson and F. N. Najm. Switching activity analysis and pre-layout activity prediction for fpgas. In ACM/IEEE International Workshop on System-Level Interconnect Prediction, pages 15-21, Monterey, CA, April 5-6 2003.

[131]

J. H. Anderson and F. N. Najm. Interconnect capacitance estimation for fpgas. In IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pages 713-718, Yokohama, Japan, January 27-30 2004.

[132]

J. H. Anderson and F. N. Najm. Low-power programmable routing circuitry for fpgas. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 602-609, San Jose, CA, November 7-11 2004.

[133]

J. H. Anderson and F. N. Najm. A novel low-power FPGA routing switch. In IEEE Custom Integrated Circuits Conference (CICC), pages 719-722, Orlando, FL, October 3-6 2004.

[134]

J. H. Anderson and F. N. Najm. Power estimation techniques for fpgas. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12(10):1015-1027, October 2004.

[135]

J. H. Anderson and F. N. Najm. Active leakage power optimization for fpgas. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25(3):423-437, March 2006.

[136]

J. H. Anderson. Geometrical approach to reduction of dynamical systems. In Proceedings of the IEE, pages 1014-1018, July 1967. Published as Proceedings of the IEE, volume 114, number 7.

[137]

N. Andrikos, L. Lavagno, D. Pandini, and C. P. Sotiriou. A fully-automated desynchronization flow for synchronous circuits. In ACM/IEEE 44th Design Automation Conference (DAC-07), pages 982-985, San Diego, CA, June 4-8 2007.

[138]

M. Anis, S. Areibi, M. Mahmoud, and M. Elmasry. Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique. In ACM/IEEE 39th Design Automation Conference (DAC-02), pages 480-485, New Orleans, LA, June 10-14 2002.

[139]

M. H. Anis, M. W. Allam, and M. I. Elmasry. Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 10(2):71-78, April 2002.

[140]

M. Anis, S. Areibi, and M. Elmasry. Design and optimization of multithreshold CMOS (MTCMOS) circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 22(10):1324-1342, October 2003.

[141]

M. Anton, I. Colonescu, E. Macii, and M. Poncino. Fast characterization of RTL power macromodels. In 8th IEEE International Conference on Electronics, Circuits and Systems, pages 1591-1594, St. Julian, Malta, September 2-5 2001.

[142]

D. A. Antonelli, D.-Z. Chen, T. J. Dysart, and X.-S. Hu. Quantum-dot cellular automata (QCA) circuit partitioning: problem modeling and solutions. In ACM/IEEE 41st Design Automation Conference (DAC-04), pages 363-368, San Diego, CA, June 7-11 2004.

[143]

D. A. Antoniadis. SOI CMOS as a mainstream low-power technology: a critical assessment. In 1997 International Symposium on Low Power Electronics and Design, pages 295-300, Monterey, CA, August 18-20 1997.

[144]

S. Ardalan, F. Yuan, and K. Raahemifar. Low power technique for delay reduction in static CMOS circuits. In The First Annual Northeast Workshop on Circuits and Systems (NEWCAS-03), pages 165-168, Montreal, Quebec, June 17-20 2003.

[145]

L. A. Arledge and W. T. Lynch. Scaling and performance implications for power supply and other signal routing constraints imposed by I/O pad limitations. In IEEE Symposium on IC/Package Design Integration, 1998.

[146]

D. B. Armstrong. On finding a nearly minimal set of fault detection tests for combinational logic nets. IEEE Transactions on Electronic Computers, EC-15(1):66-73, February 1966.

[147]

H. Arts, M. Berkelaar, and C. A. J. van Eijk. Polarized observability don't cares. In IEEE/ACM International Conference on Computer-Aided Design, pages 626-631, San Jose, CA, November 10-14 1996.

[148]

H. Arts, M. Berkelaar, and K. van Eijk. Computing observability don't cares efficiently through polarization. IEEE Transactions on Computer-Aided Design, 17(7):573-581, July 1998.

[149]

K. S. Arun and V. B. Rao. New heuristics and lower bounds for graph partitioning. In IEEE International Symposium on Circuits and Systems, pages 1172-1175, June 1991.

[150]

R. Arunachalam, K. Rajagopal, and L. T. Pileggi. TACO: Timing analysis with coupling. In Design Automation Conference, pages 266-269, Los Angeles, CA, June 5-9 2000.

[151]

R. Arunachalam, R. D. Blanton, and L. T. Pileggi. False coupling interactions in static timing analysis. In ACM/IEEE 38th Design Automation Conference (DAC-01), pages 726-731, Las Vegas, NV, June 18-22 2001.

[152]

Arvind, R. S. Nikhil, D. L. Rosenband, and N. Dave. High-level synthesis: an essential ingredient for designing complex asics. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 775-782, San Jose, CA, November 7-11 2004.

[153]

H. Asadi and M. B. Tahoori. Soft error derating computation in sequential circuits. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 497-501, San Jose, CA, November 5-9 2006.

[154]

F. H. A. Asgari and M. Sachdev. A low-power reduced swing global clocking methodology. IEEE Transactions on Very Large Scale Intergration (VLSI) Systems, 12(5):538-545, May 2004.

[155]

P. Ashar and S. Malik. Functional timing analysis using ATPG. IEEE Transactions on Computer-Aided Design, 14(8):1025-1030, August 1995.

[156]

F. Assaderaghi. Circuit styles and strategies for CMOS VLSI design on SOI. In ACM/IEEE International Symposium on Low Power Electronics and Design, pages 282-287, San Diego, CA, August 16-17 1999.

[157]

G. Astfalk, I. Lustig, R. Marsten, and D. Shanno. The interior-point method for linear programming. IEEE Software, 9(4):61-68, July 1992.

[158]

E. M. Atakov, T. S. Sriram, D. Dunnell, and S. Pizzanello. Effect of VLSI interconnect layout on electromigration performance. In IEEE International Reliability Physics Symposium, pages 348-355, Reno, NV, 1998.

[159]

W. Athas, L. Youngs, and A. Reinhart. Compact models for estimating microprocessor frequency and power. In ACM/IEEE International Symposium on Low Power Electronics and Design, pages 313-318, Monterey, California, August 12-14 2002.

[160]

W. Athas. Practical considerations of clock-powered logic. In ACM/IEEE International Symposium on Low Power Electronics and Design, pages 173-178, Italy, July 26-27 2000.

[161]

M. J. Attardo, R. Rutledge, and R. C. Jack. Statistical metallurgical model for electromigration failure in aluminum thin-film conductors. Journal of Applied Physics, 42(11):4343-4349, October 1971.

[162]

M. J. Attardo and R. Rosenberg. Electromigration damage in aluminum film conductors. Journal of Applied Physics, 41(6):2381-2386, May 1970.

[163]

L. M. Augustin. An algebra of waveforms. In L. J. M. Claesen, editor, Formal VLSI Specification and Synthesis: VLSI Design Methods, I, pages 309-318. Elsevier Science Publishers B. V. (North-Holland), New York, NY, 1990. UI : 621.395If5f.

[164]

S. Aur, C. Duvvury, and W. Hunter. Setting the trap for hot carriers. IEEE Circuits and Devices Magazine, 11(4):18-24, July 1995.

[165]

T. M. Austin. Designing robust microarchitectures. In ACM/IEEE 41st Design Automation Conference (DAC-04), pages 78-78, San Diego, CA, June 7-11 2004.

[166]

R. L. Aveyard. A boolean model for a class of discrete event systems. IEEE Transactions on Systems, Man, and Cybernetics, SMC-4(3):249-258, May 1974.

[167]

N. Azizi, A. Moshovos, and F. N. Najm. Low-leakage asymmetric-cell SRAM. In ACM/IEEE International Symposium on Low Power Electronics and Design, pages 48-51, Monterey, California, August 12-14 2002.

[168]

N. Azizi, F. N. Najm, and A. Moshovos. Low-leakage asymmetric-cell SRAM. IEEE Transactions on Very Large Scale Intergration (VLSI) Systems, 11(4):701-715, August 2003.

[169]

N. Azizi, M. M. Khellah, V. De, and F. N. Najm. Variations-aware low-power design with voltage scaling. In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages 529-534, Anaheim, CA, June 13-17 2005.

[170]

N. Azizi, M. M. Khellah, V. K. De, and F. N. Najm. Variations-aware low-power design and block clustering with voltage scaling. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 15(7):746-757, July 2007.

[171]

N. Azizi and F. N. Najm. An asymmetric SRAM cell to lower gate leakage. In IEEE International Symposium on Quality Electronic Design (ISQED), pages 534-539, San Jose, CA, March 22-24 2004.

[172]

N. Azizi and F. N. Najm. Compensation for within-die variations in dynamic logic by using body-bias. In The 3rd Annual Northeast Workshop on Circuits and Systems (NEWCAS-05), pages 167-170, Quebec City, Quebec, June 19-22 2005.

[173]

N. Azizi and F. N. Najm. Look-up table leakage reductions for fpgas. In IEEE Custom Integrated Circuits Conference (CICC), pages 187-190, San Jose, CA, September 18-21 2005.

[174]

N. Azizi and F. N. Najm. A family of cells to reduce the soft-error-rate in ternary-CAM. In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages 779-784, San Francisco, CA, July 24-28 2006.

[175]

N. Azizi and F. N. Najm. Using keeper control and body bias for fine grained threshold voltage compensation in dynamic logic. In 20th Canadian Conference on Electrical and Computer Engineering, pages 1639-1644, Vancouver, BC, April 22-26 2007.

[176]

P. Babighian, L. Benini, and E. Macii. A scalable algorithm for RTL insertion of gated clocks based on odcs computation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(1):29-42, January 2005.

[177]

P. Babighina, L. Benini, A. Macii, and E. Macii. Post-layout leakage power minimization based on distributed sleep transistor insertion. In ACM/IEEE International Symposium on Low Power Electronics and Design, pages 138-143, Newport Beach, CA, August 9-11 2004.

[178]

W. W. Bachmann and S. A. Huss. Efficient algorithms for multilevel power estimation of VLSI circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 13(2):238-254, February 2005.

[179]

M. Badaroglu, K. Tiri, S. Donnay, P. Wambacq, I. Verbauwhede, G. Gielen, and H. De Man. Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients. In ACM/IEEE 39th Design Automation Conference (DAC-02), pages 399-404, New Orleans, LA, June 10-14 2002.

[180]

M. Badaroglu, P. Wambacq, G. Van der Plas, S. Donnay, G. G. E. Gielen, and H. J. De Man. Digital ground bounce reduction by supply current shaping and clock frequency modulation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(1):65-76, January 2005.

[181]

R. I. Bahar, E. A. Frohm, C. M. Gaona, G. D. Hachtel, E. Macii, A. Pardo, and F. Somenzi. Algebraic decision diagrams and their applications. In IEEE/ACM International Conference on Computer-Aided Design, pages 188-191, Santa Clara, CA, November 7-11 1993.

[182]

R. I. Bahar, H. Cho, G. D. Hachtel, and F. Somenzi. An application of ADD-based timing analysis to combinational low power re-synthesis. In ACM/IEEE 1994 International Workshop on Low Power Design, pages 39-44, Napa, CA, April 24-27 1994.

[183]

R. I. Bahar, G. D. Hachtel, E. Macii, and F. Somenzi. A symbolic method to reduce power consumption of circuits containing false paths. In IEEE/ACM International Conference on Computer-Aided Design, pages 368-371, San Jose, CA, November 6-10 1994.

[184]

R. I. Bahar, M. Burns, G. D. Hachtel, E. Macii, H. Shin, and F. Somenzi. Symbolic computation of logic implications for technology-dependent low-power synthesis. In International Symposium on Low Power Electronics and Design, pages 163-168, Monterey, CA, August 12-14 1996.

[185]

R. Iris Bahar, H. Cho, G. D. Hachtel, E. Macii, and F. Somenzi. Symbolic timing analysis and resynthesis for low power of combinational circuits containing false paths. IEEE Transactions on Computer-Aided Design of Circuits and Systems, 16(10):1101-1115, October 1997.

[186]

R. I. Bahar and F. Somenzi. Boolean techniques for low power driven re-synthesis. In IEEE/ACM International Conference on Computer-Aided Design, pages 428-432, San Jose, CA, November 5-9 1995.

[187]

Z. Bai, P. Feldmann, and R. W. Freund. How to make theoretically passive reduced-order models passive in practice. In IEEE Custom Integrated Circuits Conference, pages 207-210, Santa Clara, CA, May 11-14 1998.

[188]

Z. Bai, R. D. Slone, W. T. Smith, and Q. Ye. Error bound for reduced system model by pade approximation via the lanczos process. IEEE Transactions on Computer-Aided Design, 18(2):133-141, February 1999.

[189]

G. Bai, S. Bobba, and I. N. Hajj. Power bus maximum voltage drop in digital VLSI circuits. In 2000 IEEE 1st International Conference on Quality Electronic Design (ISQED), pages 263-268, San Jose, CA, March 20-22 2000.

[190]

G. Bai, S. Bobba, and I. N. Hajj. Simulation and optimization of the power distribution network in VLSI circuits. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 481-486, San Jose, CA, November 5-9 2000.

[191]

G. Bai, S. Bobba, and I. N. Hajj. RC power bus maximum voltage drop in digital VLSI circuits. In IEEE International Symposium on Quality Electronic Design (ISQED), pages 205-210, San Jose, CA, March 26-28 2001.

[192]

G. Bai, S. Bobba, and I. N. Hajj. RC power bus maximum voltage drop in digital VLSI circuits. In IEEE International Symposium on Quality Electronic Design (ISQED), pages 257-258, San Jose, CA, March 26-28 2001.

[193]

G. Bai, S. Bobba, and I. N. Hajj. Static timing analysis including power supply noise effect on propagation delay in VLSI circuits. In ACM/IEEE 38th Design Automation Conference (DAC-01), pages 295-300, Las Vegas, NV, June 18-22 2001.

[194]

X. Bai, R. Chandra, S. Dey, and P. V. Srinivas. Interconnect coupling-aware driver modeling in static noise analysis for nanometer circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 23(8):1256-1263, August 2004.

[195]

X. Bai and S. Dey. High-level crosstalk defect simulation methodology for system-on-chip interconnects. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 23(9):1355-1361, September 2004.

[196]

G. Bai and I. N. Hajj. Simultaneouos switching noise and resonance analysis of on-chip power distributon network. In IEEE International Symposium on Quality Electronic Design (ISQED), pages 163-168, San Jose, CA, March 18-21 2002.

[197]

B. S. Bajwa, N. Schumann, and H. Kojima. Power analysis of a 32-bit RISC microcontroller integrated with a 16-bit DSP. In 1997 International Symposium on Low Power Electronics and Design, pages 137-142, Monterey, CA, August 18-20 1997.

[198]

S. Balachandran and D. Bhatia. A priori wirelength and interconnect estimation based on circuit characteristics. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(7):1054-1065, July 2005.

[199]

K. J. Balakrishnan and N. A. Touba. Relationship between entropy and test data compression. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 26(2):386-395, February 2007.

[200]

F. Balarin. Worst-case analysis of discrete systems. In IEEE/ACM International Conference on Computer-Aided Design, pages 347-352, San Jose, CA, November 7-11 1999.

[201]

R. Baldick, A. B. Kahng, A. Kennings, and I. L. Markov. Efficient optimization by modifying the objective function: application to timing-driven VLSI layout. IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and Applications, 48(8):947-956, August 2001.

[202]

A. Balivada, D. R. Holberg, and L. T. Pillage. Calculation and application of time-domain waveform sensitivities in asymptotic waveform evaluation. In IEEE Custom Integrated Circuits Conference, pages 8.4.1-8.4.4, 1991.

[203]

M. O. Ball and J. S. Provan. Disjoint products and efficient computation of reliability. Operations Research, 36(5):703-715, Sept.-Oct. 1988.

[204]

D. Baneres, J. Cortadella, and M. Kishinevsky. A recursive paradigm to solve boolean relations. In ACM/IEEE 41st Design Automation Conference (DAC-04), pages 416-421, San Diego, CA, June 7-11 2004.

[205]

K. Banerjee, A. Mehrotra, A. Sangiovanni-Vincentelli, and C. Hu. On thermal effects in deep sub-micron VLSI interconnects. In Design Automation Conference, pages 885-891, New Orleans, LA, June 21-25 1999.

[206]

P. Banerjee, M. Haldar, A. Nayak, V. Kim, V. Saxena, S. Parkes, D. Bagchi, S. Pal, N. Tripathi, D. Zaretsky, R. Anderson, and J. R. Uribe. Overview of a compiler for synthesizing MATLAB programs onto fpgas. IEEE Transactions on Very Large Scale Intergration (VLSI) Systems, 12(3):312-324, March 2004.

[207]

P. Banerjee and J. A. Abraham. Generating tests for physical failures in MOS logic circuits. In IEEE International Test Conference, pages 554-559, Philadelphia, PA, October 1983.

[208]

K. Banerjee and A. Mehrotra. Coupled analysis of electromigration reliability and performance in ULSI signal nets. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 158-164, San Jose, CA, November 4-8 2001.

[209]

K. Banerjee and A. Mehrotra. Analysis of on-chip inductance effects for distributed RLC interconnects. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 21(8):904-915, August 2002.

[210]

K. Banerjee and N. Srivastava. Are carbon nanotubes the future of VLSI interconnections. In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages 809-814, San Francisco, CA, July 24-28 2006.

[211]

A. Baniasadi and A. Moshovos. SEPAS: a highly accurate energy-efficient branch predictor. In ACM/IEEE International Symposium on Low Power Electronics and Design, pages 38-43, Newport Beach, CA, August 9-11 2004.

[212]

S. R. Banna, P. C. H. Chan, M. Chan, and S. K. H. Fung. Fully depleted CMOS/SOI device design guidelines for low power applications. In 1997 International Symposium on Low Power Electronics and Design, pages 301-306, Monterey, CA, August 18-20 1997.

[213]

B. R. Bannister, D. R. Melton, and G. E. Taylor. Testability of digital circuits via the spectral domain. In IEEE International Conference on Computer Design, pages 340-343, 1989.

[214]

T. S. Barnett, A. D. Singh, and V. P. Nelson. Extending integrated-circuit yield-models to estimate early-life reliability. IEEE Transactions on Reliability, 52(3):296-300, September 2003.

[215]

M. Barocci, L. Benini, A. Bogliolo, B. Ricco, and G. De Micheli. Lookup table power macro-models for behavioral library components. In IEEE Alessandro Volta Memorial Workshop on Low-Power Design, pages 173-181, Como, Italy, March 4-5 1999.

[216]

Z. Barzilai, J. L. Carter, V. S. Iyengar, I. Nair, B. K. Rosen, J. Rutledge, and G. M. Silberman. Efficient fault simulation of CMOS circuits with accurate models. In IEEE International Test Conference, pages 520-529, Sept. 8-11 1986.

[217]

D. Baschiera and B. Courtois. Testing CMOS: a challenge. VLSI Design, pages 58-62, October 1984.

[218]

R. Bashirullah, W. Liu, and R. K. Cavin. Low-power design methodology for an on-chip bus with adaptive bandwidth capability. In ACM/IEEE 40th Design Automation Conference (DAC-03), pages 628-633, Anaheim, CA, June 2-6 2003.

[219]

R. Bashirullah, W. Liu, and R. K. Cavin, III. Current-model signaling in deep submicrometer global interconnects. IEEE Transactions on Very Large Scale Intergration (VLSI) Systems, 11(3):406-417, June 2003.

[220]

R. Bashirullah, W. Liu, R. Cavin, and D. Edwards. A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12(8):876-880, August 2004.

[221]

P. Bastani, N. Callegari, L.-C. Wang, and M. S. Abadir. Ranking of unmodeled systematic timing effects. In ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU-08), pages 104-109, Monterey, CA, February 25-26 2008.

[222]

P. Bastani, K. Killpack, L.-C. Wang, and E. Chiprout. Speedpath prediction based on learning from a small set of examples. In ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU-08), pages 98-103, Monterey, CA, February 25-26 2008.

[223]

A. Basu, S.-C. Lin, V. Wason, A. Mehrotra, and K. Banerjee. Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era. In ACM/IEEE 41st Design Automation Conference (DAC-04), pages 884-887, San Diego, CA, June 7-11 2004.

[224]

M. J. Batek. Test-set preserving logic transformations. In 29th ACM/IEEE Design Automation Conference, pages 454-458, Anaheim, CA, June 8-12 1992.

[225]

K. Bazargan, S. Kim, and M. Sarrafzadeh. NOSTRADAMUS: A floorplanner of uncertain designs. In ACM/IEEE International Symposium on Physical Design, pages 18-23, Monterey, CA, April 6-8 1998.

[226]

K. Bazargan, S. Kim, and M. Sarrafzadeh. Nostradamus: A floorplanner of uncertain designs. IEEE Transactions on Computer-Aided Design, 18(4):389-397, April 1999.

[227]

M. Beattie, S. Gupta, and L. Pileggi. Hierarchical interconnect circuit models. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 215-221, San Jose, CA, November 5-9 2000.

[228]

M. Beattie, B. Krauter, L. Alatan, and L. Pileggi. Equipotential shells for efficient inductance extraction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 20(1):70-79, January 2001.

[229]

M. W. Beattie and L. T. Pileggi. Error bounds for capacitance extraction via window techniques. IEEE Transactions on Computer-Aided Design, 18(3):311-321, March 1999.

[230]

M. W. Beattie and L. T. Pileggi. Inductance 101: Modeling and extraction. In ACM/IEEE 38th Design Automation Conference (DAC-01), pages 323-328, Las Vegas, NV, June 18-22 2001.

[231]

M. W. Beattie and L. T. Pileggi. On-chip induction modeling: basics and advanced methods. IEEE Transactions on Very Large Scale Integrated (VLSI) Systems, 10(6):712-729, December 2002.

[232]

M. W. Beattie and L. T. Pileggi. Parasitics extraction with multipole refinement. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 23(2):288-292, February 2004.

[233]

D. L. Beatty and R. E. Bryant. Fast incremental circuit analysis using extracted hierarchy. In 25th ACM/IEEE Design Automation Conference, pages 495-500, Anaheim, CA, June 12-15 1988.

[234]

M. R. Becer, D. Blaauw, R. Panda, and I. N. Hajj. Pre-route noise estimation in deep submicron integrated circuits. In IEEE International Symposium on Quality Electronic Design (ISQED), pages 413-418, San Jose, CA, March 18-21 2002.

[235]

M. R. Becer, D. Blaauw, I. Algor, R. Panda, C. Oh, V. Zolotov, and I. N. Hajj. Post-route gate sizing for crosstalk noise reduction. In IEEE International Symposium on Quality Electronic Design (ISQED), pages 171-176, San Jose, CA, March 24-26 2003.

[236]

M. R. Becer, D. Blaauw, R. Panda, and I. N. Hajj. Early probabilistic noise estimation for capacitively coupled interconnects. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 22(3):337-345, March 2003.

[237]

M. R. Becer, D. Blaauw, H. Algor, R. Panda, C. Oh, V. Zolotov, and I. N. Hajj. Postroute gate sizing for crossing noise reduction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 23(12):1670-1677, December 2004.

[238]

M. Becer, V. Zolotov, R. Panda, A. Grinshpon, I. Algor, R. Levy, and C. Oh. Pessimism reduction in crosstalk noise aware STA. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD-05), pages 954-961, San Jose, CA, November 6-10 2005.

[239]

M. Becer and I. N. Hajj. An analytical model for delay and crosstalk estimation in interconnects. In 7th IEEE International Conference on Electronics, Circuits and Systems, pages 831-835, Beirut, Lebanon, December 17-19 2000.

[240]

M. Becer and I. N. Hajj. An analytical model for delay and crosstalk estimation with application to decoupling. In 2000 IEEE 1st International Conference on Quality Electronic Design (ISQED), pages 51-57, San Jose, CA, March 20-22 2000.

[241]

P. Beckett. A low-power reconfigurable logic array based on double-gate transistors. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 16(2):115-123, February 2008.

[242]

F. Beeftink, P. Kudva, D. Kung, and L. Stok. Gate-size selection for standard cell libraries. In IEEE/ACM International Conference on Computer-Aided Design, pages 545-550, San Jose, CA, November 8-12 1998.

[243]

S. De Beer, M. du Plessis, and E. Seevinck. An SRAM array based on a four-transistor CMOS SRAM cell. IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and Applications, 50(9):1203-1208, September 2003.

[244]

P. A. Beerel, K. Y. Yun, S. M. Nowick, and P-C. Yeh. Estimation and bounding of energy consumption in burst-mode control circuits. In IEEE/ACM International Conference on Computer-Aided Design, pages 26-33, San Jose, CA, November 5-9 1995.

[245]

C. C. Beh, K. H. Arya, C. E. Radke, and K. E. Torku. Do stuck fault models reflect manufacturing defects. In IEEE International Test Conference, pages 35-42, 1982.

[246]

F. Beichelt and P. Tittmann. A generalized reduction method for the connectedness probability of stochastic networks. IEEE Transactions on Reliability, 40(2):198-203, June 1991.

[247]

B. A. Beitman and A. Ito. Generation of electromigration ground rules utilizing monte carlo simulation methods. IEEE Transactions on Semiconductor Manufacturing, 4(1):63-66, February 1991.

[248]

V. Beiu, S. Aunet, J. Nyathi, R. R. Rydberg, III, and W. Ibrahim. Serial addition: locally connected architectures. IEEE Transactions on Circuits and Systems, 54(11):2564-2579, November 2007.

[249]

N. Bellas, I. N. Hajj, C. D. Polychronopoulos, and G. Stamoulis. Architectural and compiler techniques for energy reduction in high-performance microprocessors. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 8(3):317-326, June 2000.

[250]

N. E. Bellas, I. N. Hajj, and C. D. Polychronopoulos. Using dynamic cache management techniques to reduce energy in general purpose processors. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 8(6):693-708, December 2000.

[251]

G. Beltrame, C. Brandolese, W. Fornaciari, F. Salice, D. Sciuto, and V. Trianni. An assembly-level execution-time model for pipelined architectures. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 195-200, San Jose, CA, November 4-8 2001.

[252]

L. Bening. A two-state methodology for RTL logic simulation. In Design Automation Conference, pages 672-677, New Orleans, LA, June 21-25 1999.

[253]

L. Benini, M. Favalli, P. Olivo, and B. Ricco. A novel approach to cost-effective estimate of power dissipation in CMOS ics. In European Design Automation Conference (EDAC), pages 354-360, 1993.

[254]

L. Benini, M. Favalli, and B. Ricco. Analysis of hazard contributions to power dissipation in CMOS ics. In ACM/IEEE 1994 International Workshop on Low Power Design, pages 27-32, Napa, CA, April 24-27 1994.

[255]

L. Benini, P. Siegel, and G. De Micheli. Saving power by synthesizing gate clocks for sequential circuits. IEEE Design and Test of Computers, 11(4):32-40, December 1994.

[256]

L. Benini, G. De Micheli, E. Macii, M. Poncino, and S. Quer. System-level power optimization of special purpose applications: The beach solution. In 1997 International Symposium on Low Power Electronics and Design, pages 24-29, Monterey, CA, August 18-20 1997.

[257]

L. Benini, G. De Micheli, E. Macii, M. Poncino, and R. Scarsi. Fast power estimation for deterministic input streams. In IEEE/ACM International Conference on Computer-Aided Design, pages 494-501, San Jose, CA, November 9-13 1997.

[258]

L. Benini, A. Bogliolo, S. Cavallucci, and B. Ricco. Monitoring system activity for OS-directed dynamic power management. In ACM/IEEE International Symposium on Low Power Electronics and Design, pages 185-190, Monterey, CA, August 10-12 1998.

[259]

L. Benini, A. Bogliolo, and G. De Micheli. Dynamic power management of electronic systems. In IEEE/ACM International Conference on Computer-Aided Design, pages 696-702, San Jose, CA, November 8-12 1998.

[260]

L. Benini, R. Hodgson, and P. Siegel. System-level power estimation and optimization. In ACM/IEEE International Symposium on Low Power Electronics and Design, pages 173-178, Monterey, CA, August 10-12 1998.

[261]

L. Benini, G. De Micheli, E. Macii, M. Poncino, and S. Quer. Power optimization of core-based systems by address bus encoding. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 6(4):554-562, December 1998.

[262]

L. Benini, A. Macii, E. Macii, M. Poncino, and R. Scarsi. Synthesis of low-overhead interfaces for power-efficient communication over wide buses. In Design Automation Conference, pages 128-133, New Orleans, LA, June 21-25 1999.

[263]

L. Benini, A. Bogliolo, and G. De Micheli. A survey of design techniques for system-level dynamic power management. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 8(3):299-316, June 2000.

[264]

L. Benini, A. Macii, E. Macii, M. Poncino, and R. Scarsi. Architectures and synthesis algorithms for power efficient bus-interfaces. IEEE Transactions on Computer-Aided Design, 19(9):969-980, September 2000.

[265]

L. Benini, A. Macii, and M. Poncino. A recursive algorithm for low-power memory partitioning. In ACM/IEEE International Symposium on Low Power Electronics and Design, pages 78-83, Italy, July 26-27 2000.

[266]

L. Benini, G. De Micheli, A. Macii, E. Macii, M. Poncino, and R. Scarsi. Glitch power minimization by selective gate freezing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 8(3):287-298, June 2000.

[267]

L. Benini, G. De Micheli, E. Macii, M. Poncino, and R. Scarsi. A multilevel engine for fast power simulation of realistic input streams. IEEE Transactions on Computer-Aided Design, 19(4):459-472, April 2000.

[268]

L. Benini, G. De Micheli, A. Lioy, E. Macii, G. Odasso, and M. Poncino. Synthesis of power-managed sequential components based on computational kernel extraction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 20(9):1118-1131, September 2001.

[269]

L. Benini, G. De Micheli, and E. Macii. Designing low-power circuits: practical recipes. IEEE Circuits and Systems Magazine, 1(1):6-25, Q1 2001.

[270]

L. Benini, A. Macii, E. Macii, and M. Poncino. Minimizing memory acess energy in embedded systems by selective instruction compression. IEEE Transactions on Very Large Scale Integrated (VLSI) Systems, 10(5):521-531, October 2002.

[271]

L. Benini, A. Galati, and A. Macii. Energy-efficient data scrambling on memory-processor interfaces. In ACM/IEEE International Symposium on Low Power Electronics and Design, pages 26-29, Seoul, Korea, August 25-27 2003.

[272]

L. Benini, D. Bruni, A. Macii, and E. Macii. Memory energy minimization by data compression: algorithms, architectures and implementation. IEEE Transactions on Very Large Scale Intergration (VLSI) Systems, 12(3):255-268, March 2004.

[273]

L. Benini and G. De Micheli. State assignment for low power dissipation. In IEEE 1994 Custom Integrated Circuits Conference, pages 136-139, San Diego, CA, May 1-4 1994.

[274]

L. Benini and G. De Micheli. Automatic synthesis of low-power gated-clock finite-state machines. IEEE Transactions on Computer-Aided Design, 15(6):630-643, June 1996.

[275]

L. Benini and G. De Micheli. System level power optimization: techniques and tools. In ACM/IEEE International Symposium on Low Power Electronics and Design, pages 288-293, San Diego, CA, August 16-17 1999.

[276]

J. Benkoski and A. J. Strojwas. A new approach to hierarchical and statistical timing simulations. IEEE Transactions on Computer-Aided Design, CAD-6(6):1039-1052, November 1987.

[277]

J. Benkoski and A. J. Strojwas. The role of timing verification in layout synthesis. In 28th ACM/IEEE Design Automation Conference, pages 612-619, San Francisco, CA, June 17-21 1991.

[278]

T. R. Bennett, J. M. Booker, S. Keller-McNulty, and N. D. Singpurwalla. Testing the untestable: reliability in the 21st century. IEEE Transactions on Reliability, 52(1):118-124, March 2003.

[279]

M. Benoit, S. Taylor, D. Overhauser, and S. Rochel. Power distribution in high-performance design. In ACM/IEEE International Symposium on Low Power Electronics and Design, pages 274-278, Monterey, CA, August 10-12 1998.

[280]

R. A. Bergamaschi, D. Brand, L. Stok, M. Berkelaar, and S. Prakash. Efficient use of large don't cares in high-level and logic synthesis. In IEEE/ACM International Conference on Computer-Aided Design, pages 272-278, San Jose, CA, November 5-9 1995.

[281]

R. A. Bergamaschi and Y. W. Jiang. State-based power analysis for systems-on-chip. In ACM/IEEE 40th Design Automation Conference (DAC-03), pages 638-641, Anaheim, CA, June 2-6 2003.

[282]

R. A. Bergamaschi and W. R. Lee. Designing systems-on-chip using cores. In Design Automation Conference, pages 420-425, Los Angeles, CA, June 5-9 2000.

[283]

R. A. Bergamaschi. Behavioral network graph unifying the domains of high-level and logic synthesis. In Design Automation Conference, pages 213-218, New Orleans, LA, June 21-25 1999.

[284]

R. Bergamaschi. The A to Z of socs. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 791-798, San Jose, CA, November 10-14 2002.

[285]

J. P. Bergmann and M. A. Horowitz. Vex - A CAD toolbox. In Design Automation Conference, pages 523-528, New Orleans, LA, June 21-25 1999.

[286]

M. R. C. M. Berkelaar, P. H. W. Buurman, and J. A. G. Jess. Computing the entire active area/power consumption versus delay tradeoff curve for gate sizing with a piecewise linear simulator. IEEE Transactions on Computer-Aided Design, 15(11):1423-1434, November 1996.

[287]

D. Berleant and J. Zhang. Bounding the times to failure of 2-component systems. IEEE Transactions on Reliability, 53(4):542-550, December 2004.

[288]

C. Leonard Berman. Circuit width, register allocation, and ordered binary decision diagrams. IEEE Transactions on Computer-Aided Design, 10(8):1059-1066, August 1991.

[289]

G. Bernacchia and M. C. Papaefthymiou. Analytical macromodeling for high-level power estimation. In IEEE/ACM International Conference on Computer-Aided Design, pages 280-283, San Jose, CA, November 7-11 1999.

[290]

R. Bernardini and G. Cortelazzo. Tools for designing chaotic systems for secure random number generation. IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and Applications, 48(5):552-565, May 2001.

[291]

A. Bernasconi, V. Ciriani, F. Luccio, and L. Pagli. Three-level logic minimization based on function regularities. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 22(8):1005-1016, August 2003.

[292]

K. Bernstein, J. E. Bertsch, W. F. Clark, J. J. Ellis-Monaghan, L. G. Heller, and E. J. Nowak. Practical performance/power alternatives within an existing CMOS technology generation. In International Symposium on Low Power Electronics and Design, pages 365-370, Monterey, CA, August 12-14 1996.

[293]

K. Bernstein, P. Andry, J. Cann, P. Emma, D. Greenberg, W. Haensch, M. Ignatowski, S. Koester, J. Magerlein, R. Puri, and A. Young. Interconnects in the third dimension: design and process challenges for 3d ics. In ACM/IEEE 44th Design Automation Conference (DAC-07), pages 562-567, San Diego, CA, June 4-8 2007.

[294]

G. M. Bernstein and M. A. Lieberman. Secure random number generation using chaotic circuits. IEEE Transactions on Circuits and Systems, 37(9):1157-1164, September 1990.

[295]

V. Bertacco and M. Damiani. The disjunctive decomposition of logic functions. In IEEE/ACM International Conference on Computer-Aided Design, pages 78-82, San Jose, CA, November 9-13 1997.

[296]

D. Bertozzi, L. Benini, and B. Ricco'. Parametric timing and power macromodels for high level simulation of low-swing interconnects. In ACM/IEEE International Symposium on Low Power Electronics and Design, pages 307-312, Monterey, California, August 12-14 2002.

[297]

D. Bertozzi, L. Benini, and G. De Micheli. Error control schemes for on-chip communication links: the energy-reliability tradeoff. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(6):818-831, June 2005.

[298]

R. M. Bevensee. Probabilistic potential theory applied to electrical engineering problems. In Proceedings of the IEEE, pages 423-437, April 1973. Published as Proceedings of the IEEE, volume 61, number 4.

[299]

W. T. Beyene. Application of artifical neural networks to statistical analysis and nonlinear modeling of high-speed interconnect systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 26(1):166-176, January 2007.

[300]

D. Bhaduri, S. K. Shukla, P. S. Graham, and M. B. Gokhale. Reliability analysis of large circuits using scalable techniques and tools. IEEE Transactions on Circuits and Systems, 54(11):2447-2460, November 2007.

[301]

S. Bhanja and N. Ranganathan. Dependency preserving probabilistic modeling of switching activity using bayesian networks. In ACM/IEEE 38th Design Automation Conference (DAC-01), pages 209-214, Las Vegas, NV, June 18-22 2001.

[302]

S. Bhanja and N. Ranganathan. Switching activity estimation of VLSI circuits using bayesian networks. IEEE Transactions on Very Large Scale Intergration (VLSI) Systems, 11(4):558-567, August 2003.

[303]

S. Bhanja and N. R. Ranganathan. Cascaded bayesian inferencing for switching activity estimation with correlated inputs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12(12):1360-1370, December 2004.

[304]

K. Bharath, E. Engin, M. Swamminathan, K. Uriu, and T. Yamada. Computationally efficient power integrity simulation for system-on-package applications. In ACM/IEEE 44th Design Automation Conference (DAC-07), pages 612-617, San Diego, CA, June 4-8 2007.

[305]

M. Bhardwaj, R. Min, and A. P. Chandrakasan. Quantifying and enhancing power awareness of VLSI systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 9(6):757-772, December 2001.

[306]

S. Bhardwaj, S. B. K. Vrudhula, and D. Blaauw. Estimation of signal arrival times in the presence of delay noise. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 418-422, San Jose, CA, November 10-14 2002.

[307]

S. Bhardwaj, S. B. K. Vrudhula, and D. Blaauw. TAU: timing analysis under uncertainty. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 615-620, San Jose, CA, November 9-13 2003.

[308]

S. Bhardwaj, S. Vrudhula, and D. Blaauw. Probability distribution of signal arrival times using bayesian networks. IEEE Transactions on Computer-A