Midterm Examination - October 1997
ECE352F - Computer Organization
Examiner - Paul Chow
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PC.out, Y.intransfers the contents of the PC to the Y register.
add r1,r2,r3 % r3 <- r1 + r2give the microcode sequences using the single-bus structure of Figure 1 and your three-bus structure. Remember to update the PC and be sure to comment your microcode clearly.
Comment on the differences between the microcode for the two structures, and the hardware needed to implement the two structures.
Show how the PIC can be connected to the printer control lines and data bus.
Give a timing diagram to specify the required actions of C1, C2, and C3 to reliably transfer data on PD0-7 using asynchronous control with full handshaking. Your timing diagram should show all of the control signals on the bus, and the times when data must be valid on the data bus.
Assume that you have full adder circuits that have inputs xi, yi, and ci. The outputs, si and ci+1, are stable after 2 gate delays from the inputs. There are 4-bit carry-lookahead (CLA) units where the Pi and Givalues are available after 1 gate delay.
A 16x16 multiplier is to be built. Compare the delay using an array implementation and an implementation using a carry-save adder tree. You may use as much CLA logic as you can to make long adders faster. If you need other gates, assume that they have a delay of 1.
Show clearly with diagrams the structure of your multipliers and how you are deriving your delays. Structure does not mean that you have to draw the whole circuit, just enough to show how it is being put together.