-------------------------------------------------------------------------------
--
-- This is an example of trying to combine the outputs of a circuit with the
-- definition of the FSM.  This version separates the output from the state
-- machine so that there is no extra state inferred.
-- 
-- Paul Chow
-- Department of Electrical and Computer Engineering
-- University of Toronto
--
-- October 1998
--
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity fsm_good is
    port(
         iClk           : in  STD_LOGIC;
         iReset         : in  STD_LOGIC;
         iX,iY          : in  STD_LOGIC;
         oOutput        : out STD_LOGIC
         );
end fsm_good;


architecture RTL of fsm_good is
    type StateTypes is (StateA,StateB);
    signal State : StateTypes;

begin --  RTL

    GOOD: process (iClk,iReset,iX,iY,State)
        
    begin --  GOOD

        if(iReset = '1') then
            State <= StateA;
        elsif (iClk'event and iClk = '1') then
            case State is
                when StateA =>
                    State <= StateB;
                when StateB =>
                    State <= StateA;
            end case; --  State
        end if;

        case State is
            when StateA =>
                oOutput <= iX;
            when StateB =>
                oOutput <= iY;
        end case; --  State

    end process GOOD;
    
end RTL;  -- of fsm_good