Labs

Optimization Requirements

• Lab 4:
  • Area: 154 LEs (maximum)
  • Speed: 18 MHz (minimum)
• Lab 5:
  • Part 1 Area: 60 LEs (maximum) (register)
  • Part 2 Area: 100 LEs (maximum) (sram controller)
• Lab 6:
  • Area: 70 LEs (maximum)
  • Speed: 46 MHz (minimum)
• Project Part 1:
  • Area: 460 LEs (maximum)
  • Speed: 16 MHz (minimum)
• Project Part 2:
  • Area: 580 LEs (maximum)
  • Speed: 16 MHz (minimum)

Descriptions

• Lab 1: Lab M7 "(DUART and Interrupts) Input and Output Using Polling and Interrupts".
• Lab 2: Lab M10 "Parallel I/O and the LEGO Motors and Sensors".
• Lab 3: Lab M12 "Interrupt-Driven I/O Using the LEGO Sensors".
• Lab 4: Lab F2 "Hierarchical Design".
  • Remember that you are going to be using Quartus II in the labs (not Max+Plus II as indicated in your Ultragizmo manuals).
  • For additional information on Quartus II, refer to this link: CAD Tools .
  • Use the following files to get yourself started in Quartus II:
    • A quartus project file: wrapper10k100.qpf . (for Quartus II v.4.1)
    • A quartus compiler settings file: wrapper10k100.csf . The quartus compiler settings file specifies the chip used in the lab (BA3165), EPF10K100GC503-3, and the pin assignments used by the chip.
    • A top level verilog file: wrapper10k100.v .
    • If you prefer vhdl then use the following top level vhdl file: wrapper10k100.vhd . The quartus project is setup to use a verilog file; if you are going to be using vhdl then delete the verilog file after loading the project and add the vhdl file instead.
    • Note that the vhdl/verilog wrapper file that is provided specifies all pins except "leds" as input. You should change the direction (in/out/inout) of the pins as required by your design.
    • Also if you want to test your design in the design center please use these files: wrapper10k70.qpf , wrapper10k70.csf , and wrapper10k70.v , or wrapper10k70.vhd . Please to go the assignments menu, and check that the assigned device is the Flex10K - EPF10K70GC503-4 Device.
    • Note: If the board lights up random leds when you program it, the pins assignments are probably missing. If this happens you will need to close your project, delete all the file in your project directory (except your .v or .vhd files) and redownload the .qpf and .csf files. Make sure that the .csf does not get the extension .txt when you try to download it.
• Lab 5: Lab F5 "Data Transfers on the M68000", parts 1 and 2 only. During the lab you will be asked to make a modification to one of the two designs.
• Lab 6: "Reaction Timer". Here is a PDF file and PS file that describes the lab.
• Project: "Simple Processor Implementation". Here is a PDF file and a PS file that describes the lab.
  • If you are using VHDL then use the following files to get you started:
    • top.vhd
    • proc.vhd
  • If you are using Verilog then use the following files:
    • top.v
    • proc.v
  • The memory initialization file (needed by 'top') is common to both VHDL and Verilog: test.mif .
  • Note that the inputs to the ram internal to the FLEX chip is already registered. That is, 'ram_data_in', 'sram_ad' and 'we' are being registered in the 'lpm_ram_dq' module instantiated by the top module. Make sure you don't register these signals when using the internal ram. However, when using the external SRAM chip, these signals should be registered as normal.