Lab Marking Scheme

Assembly Labs (Labs 1-3)

Prep	2
Functionality	6

Total	8

Verilog Labs (Labs 4-9)

Prep	2
Functionality	6
Optimizations	2

Total	10

Lab 7 (Project Part 1) will also be marked on coding style. This will have a mark out of 10, therefore making the total for that lab 20 marks. Please email both TAs with your Verilog or VHDL files (Only send the HDL text files. Do not send your entire lab directory).

Coding Style

Appropriate design partitioning (must be modularized, hierarchical, shows clear schematic partitioning)	2
Appropriate level of coding abstraction (can you see the flip/flops in your design?)	2
Appropriate sequential logic implementation (no gated clocks, appropriate resets, no latches)	4
Commenting/Naming of modules	2

Total	10

Explanation of Marks

Prep: Marks are given for the amount of preparation done for the lab. 0 - for no prep, 1 - for some prep, and 2 - for a complete prep.
Functionality: Marks are given for the amount of the lab that was completed and working.
Optimizations: This will be graded by looking the area usage and circuit speed. Area usage is determined by the number of logic elements used, and the circuit speed is determined by the maximum frequecy (FMax) of the circuit. One mark will be given if your circuit uses less logic elements than a modest design. One mark will be given if your circuit have a greater maximum frequency than a modest design. The logic element usage and maximum frequency for a modest design (which should be easy to beat with a little planning) will be posted no later than one week before the lab. You can use the optimize for area and optimize for speed to get your best results. Beware, get something working before you worry about the optimizations.

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