Lab Marking Scheme


Assembly Labs (Labs 1-3)

Prep 2
Functionality 6

Total 8

Verilog Labs (Labs 4-9)

Prep 2
Functionality 6
Optimizations 2

Total 10

Lab 7 (Project Part 1) will also be marked on coding style. This will have a mark out of 10, therefore making the total for that lab 20 marks. Please email both TAs with your Verilog or VHDL files (Only send the HDL text files. Do not send your entire lab directory).

Coding Style

Appropriate design partitioning (must be modularized, hierarchical, shows clear schematic partitioning) 2
Appropriate level of coding abstraction (can you see the flip/flops in your design?) 2
Appropriate sequential logic implementation (no gated clocks, appropriate resets, no latches) 4
Commenting/Naming of modules 2

Total 10

Explanation of Marks


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