//////////////////////////////////////////////////////////////////////////////
//
//    File Name:  proc.v
//      Version:  1
//         Date:  Oct26/04
//       Author:  Chris Comis
//  Description:  Processor implementation
//
//////////////////////////////////////////////////////////////////////////////



module proc 
  (
   
   // clock and reset
   clk,
   reset_b, // active low reset
   
   // enable for clock 
   cnt_enable,
   
   // RAM
   address, 
   data_in, 
   data_out, 
   sram_read, 
   sram_write,
   
   // switches and LEDs
   port_in, 
   port_out, 

   // debug ports
   o_r0, o_r1, o_r2, o_r3, o_instr);
   

///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
   
   // clock and reset
   input clk, reset_b;
   // enable for clock 
   input cnt_enable;
   // RAM
   output [8:0] address;
   input [15:0] data_in;
   output [15:0] data_out;
   output        sram_read, sram_write;
   // switches and LEDs
   input [7:0]   port_in;
   output [7:0]  port_out;

   // debug ports
   output [15:0] o_r0, o_r1, o_r2, o_r3;
   output [3:0]  o_instr;

   

   
///////////////////////////////////////////////////////////////////////////////
// Parameter Declarations
///////////////////////////////////////////////////////////////////////////////

   // states
   parameter     INIT_0 = 3'b000,
		 INIT_1 = 3'b001,
		 INIT_2 = 3'b010,
		 INIT_3 = 3'b011,
		 INIT_4 = 3'b100;
   // instructions (may come in handy later)
   parameter     MOVI  = 4'b0000,
		 MOVE  = 4'b0001,
		 LOAD  = 4'b0010,
		 STOR  = 4'b0011,
		 ADD   = 4'b0100,
		 SUB   = 4'b0101,
		 HALT  = 4'b0110,
		 BNE   = 4'b0111,
		 MVIN  = 4'b1000,
		 MVOUT = 4'b1001,
		 MVCNT = 4'b1010,
		 MVCFG = 4'b1011;

///////////////////////////////////////////////////////////////////////////////
// Wire and Register Declarations
///////////////////////////////////////////////////////////////////////////////

   // state registers
   reg [02:00]   Present_State, Next_State;
   // Registers for r0-r3, pc, ir, temp, z, port_in, port_out and config (as shown in the diagram)
   // You could simply declare them as registers (as seen here)
   // An alternative way (and what I did) would be to use the lpm register or create simple register modules:
   //    - a 16-bit simple register module
   //    - an 8-bit simple register module
   //    - a 1-bit simple register module
   // Then, instantiate one of these register modules for each of the registers as seen in the diagram 
   reg [15:00] r0_reg;
   reg [15:00] r1_reg;
   reg [15:00] r2_reg;
   reg [15:00] r3_reg;
   reg [15:00] pc_reg;
   reg [15:00] ir_reg;
   reg [15:00] temp_reg;
   reg [15:00] z_reg;
   reg         s_reg;
   reg [07:00] port_in_reg;
   reg [07:00] port_out_reg;
   reg [07:00] config_reg;
   wire [03:00] op;
   
   

///////////////////////////////////////////////////////////////////////////////
// Finite State Machine
///////////////////////////////////////////////////////////////////////////////

   // Combinational logic portion
   // Note that the following always block translates to only
   // combinational logic (there will not be any D-flip/flops)
   always @(Present_State) begin  // sensitivity lists for combinational always blocks should include ALL inputs
      case (Present_State)
        // initialization states
        INIT_0:
          begin
          end
        INIT_1:
          begin
          end
        INIT_2:
          begin
          end
        INIT_3:
          begin
          end
        // individual instruction implementation
	INIT_4: begin
	   case (op)
	     MOVI:
               begin
               end
	     MOVE:
               begin
               end
	     LOAD:
               begin
               end
	     STOR:
               begin
               end
	     ADD:
               begin
               end
	     SUB:
               begin
               end
	     HALT:
               begin
               end
	     default: ;
	   endcase
	end
      endcase
   end
   
   // Sequential logic portion
   // Note that the following is sequential logic
   // We basically create a register (a series of D-flip/flops) that transitions
   // Present_State <= Next_State on a rising edge of the clock
   // Note also that because we have D-flip/flops, we must have some sort of reset
   always @(posedge clk or negedge reset_b)
     begin
        if (reset_b == 1'b0) 
          Present_State <= INIT_0;
      else
        begin
           Present_State <= Next_State;
        end
   end

   
///////////////////////////////////////////////////////////////////////////////
// Component Instantiation
///////////////////////////////////////////////////////////////////////////////

   /* ??registers?? (if not done above) */
   
   /* encoder and multiplexor */
   
   /* alu */
   
   /* status register */
   
   /* sram interface */
   
   /* registers for sram_addr, sram_data, sram_read, sram_write */
   
   /* counter */

   
endmodule