library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity proc is
   port( clk      		: in  std_logic;
   	 cnt_clk   		: in  std_logic;
         address  		: out std_logic_vector(  8 downto 0 );
         data_in  		: in  std_logic_vector( 15 downto 0 );
         data_out 		: out std_logic_vector( 15 downto 0 );
         sram_read		: out std_logic;
         sram_write		: out std_logic;
         port_in 		: in  std_logic_vector(  7 downto 0 );
         port_out 		: out std_logic_vector(  7 downto 0 );
         o_r0, o_r1, o_r2, o_r3 : out std_logic_vector( 15 downto 0 );
         o_instr		: out std_logic_vector(  3 downto 0 );
         o_status		: out std_logic);
end proc;

architecture behav of proc is

   -- useful constants
   constant MOVI  : std_logic_vector( 3 downto 0 ) := "0000";
   constant MOVE  : std_logic_vector( 3 downto 0 ) := "0001";
   constant LOAD  : std_logic_vector( 3 downto 0 ) := "0010";
   constant STOR  : std_logic_vector( 3 downto 0 ) := "0011";
   constant ADD   : std_logic_vector( 3 downto 0 ) := "0100";
   constant SUB   : std_logic_vector( 3 downto 0 ) := "0101";
   constant HALT  : std_logic_vector( 3 downto 0 ) := "0110";
   constant BNE   : std_logic_vector( 3 downto 0 ) := "0111";
   constant MVIN  : std_logic_vector( 3 downto 0 ) := "1000";
   constant MVOUT : std_logic_vector( 3 downto 0 ) := "1001";
   constant MVCNT : std_logic_vector( 3 downto 0 ) := "1010";
   constant MVCFG : std_logic_vector( 3 downto 0 ) := "1011";

   type state_type is ( T0, T1, T2, T3, T4 );
   signal TC, TN : state_type;
   signal IR                    : std_logic_vector( 15 downto 0 );
   signal I                     : std_logic_vector(  3 downto 0 );

begin

   -- IR is assumed to be the output of the IR
   I     <= IR( 15 downto 12 );

   -- state machine for control circuit
   process( TC )
   begin
      -- default values of signals
      case TC is
      when T0 =>
      when T1 =>
      when T2 =>
      when T3 =>
      when T4 =>
         case I is
         when MOVI => 
         when MOVE => 
         when LOAD => 
         when STOR => 
         when ADD  =>
         when SUB  =>
         when HALT => 
         when others =>
         end case;
      -- add states as needed
      end case;
   end process;

   process( clk )
   begin
      if clk'event and clk='1' then
         TC <= TN;
      end if;
   end process;

   -- registers for R0-R3, PC, IR, Temp, Z, PortIN, PortOUT and Config
   
   -- encoder and multiplexor

   -- ALU

   -- status register

   -- SRAM interface
   -- registers for SramAddr, SramData, Sram_Read, Sram_Write

   -- counter

end behav;