//////////////////////////////////////////////////////////////////////////////
//
//    File Name:  top.v
//      Version:  1
//         Date:  Oct26/04
//       Author:  Chris Comis
//  Description:  Top level for processor
//                Instantiate processor, memory, counter
//
//////////////////////////////////////////////////////////////////////////////


module top 
  (
   clk,
   reset_b,
   port_in, 
   port_out,

   // debug ports
   o_address, o_sram_ad, 
   o_ram_data_out, o_ram_data_in,
   o_ram_read, o_ram_write,
   o_r0, o_r1, o_r2, o_r3, o_instr

   );

   // ports
   input clk;
   input reset_b;

   // switches, leds
   input [07:00] port_in;
   output [07:00] port_out;

   // debug ports
   output [8:0] o_address;
   output [4:0] o_sram_ad;
   output [15:0] o_ram_data_out, o_ram_data_in;
   output        o_ram_read, o_ram_write;
   output [15:0] o_r0, o_r1, o_r2, o_r3;
   output [3:0]  o_instr;

   
   // wires and registers between lpm_ram and processor
   wire [15:0]   ram_data_out, ram_data_in;
   wire          ram_read, ram_write;
   wire          cnt_enable;
   wire [8:0]    address;
   wire [4:0]    sram_ad;

   // assignments for lpm_ram   
   assign        sram_ad[3:0] = address[3:0];
   assign        sram_ad[4] = ~address[8];

   // some debug assignments
   assign        o_ram_data_out = ram_data_out;
   assign        o_ram_data_in = ram_data_in;
   assign        o_ram_read = ram_read;
   assign        o_ram_write = ram_write;
   
   // instantiation of processor
   proc my_proc
     (
      .clk(clk),
      .reset_b(reset_b),
      .cnt_enable(cnt_enable), 
      .address(address), 
      .data_in(ram_data_out),
      .data_out(ram_data_in),
      .sram_read(ram_read),
      .sram_write(ram_write),
      .port_in(port_in),
      .port_out(port_out),

      // remaining debug assignments
      .o_r0(o_r0), 
      .o_r1(o_r1), 
      .o_r2(o_r2), 
      .o_r3(o_r3),
      .o_instr(o_instr)
      );

   
   // instantation of lpm_ram (for first week only)
   lpm_ram_dq ram 
     (
      .data(ram_data_in), 
      .address(sram_ad),
      .we(ram_write), 
      .inclock (clk),
      .q(ram_data_out)
      );
   defparam      ram.LPM_WIDTH = 16;
   defparam      ram.LPM_WIDTHAD = 5;
   defparam      ram.LPM_FILE = "test.mif";
   defparam      ram.LPM_INDATA = "REGISTERED";
   defparam      ram.LPM_ADDRESS_CONTROL = "REGISTERED";
   defparam      ram.LPM_OUTDATA = "UNREGISTERED";

  /* instantiation of clock divider (for cnt_enable) */
   
endmodule