library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library lpm;
use lpm.lpm_components.all;

-- Note that various outputs useful for debugging are provided in the entity 
-- delcaration and in the declaration of the "proc" component.  These outputs
-- are preceeded with a "o_".

entity top is
   port( clk : in std_logic; 
         o_address 			: out std_logic_vector( 8 downto 0 );
         o_sram_ad 			: out std_logic_vector( 4 downto 0 );
         o_ram_data_out, o_ram_data_in 	: out std_logic_vector( 15 downto 0 );
         o_ram_read, o_ram_write 	: out std_logic;
         port_in 			: in  std_logic_vector( 7 downto 0 );
         port_out 			: out  std_logic_vector( 7 downto 0 );
         o_r0, o_r1, o_r2, o_r3		: out std_logic_vector( 15 downto 0 );
         o_instr  			: out  std_logic_vector( 3 downto 0 );
         o_status			: out std_logic);
end top;

architecture behav of top is

   component proc
   port( clk      		: in  std_logic;
         cnt_clk		: in  std_logic;
         address  		: out std_logic_vector(  8 downto 0 );
         data_in  		: in  std_logic_vector( 15 downto 0 );
         data_out 		: out std_logic_vector( 15 downto 0 );
         sram_read		: out std_logic;
         sram_write		: out std_logic;
         port_in 		: in  std_logic_vector(  7 downto 0 );
         port_out 		: out std_logic_vector(  7 downto 0 );
         o_r0, o_r1, o_r2, o_r3 : out std_logic_vector( 15 downto 0 );
         o_instr		: out std_logic_vector(  3 downto 0 ); 
         o_status		: out std_logic);
   end component;

   signal address : std_logic_vector( 8 downto 0 );
   signal ram_data_out, ram_data_in : std_logic_vector( 15 downto 0 );
   signal cnt_clk, ram_read, ram_write : std_logic;
   signal sram_ad : std_logic_vector( 4 downto 0 );

begin

   o_sram_ad <= sram_ad;
   o_ram_data_out <= ram_data_out;
   o_ram_data_in <= ram_data_in;
   o_address <= address;
   o_ram_read <= ram_read;
   o_ram_write <= ram_write;

   sram_ad( 3 downto 0 ) <= address( 3 downto 0 );
   sram_ad( 4 ) <= not address( 8 );

   RAM: lpm_ram_dq generic map ( lpm_width => 16,
                                 lpm_widthad => 5,
                                 lpm_file => "test.mif",
                                 lpm_indata => "REGISTERED",
                                 lpm_address_control => "REGISTERED",
                                 lpm_outdata => "UNREGISTERED" )
        port map ( data => ram_data_in,
                   address => sram_ad,
                   we => ram_write,
				   inclock => clk,
                   q => ram_data_out );

   -- Instantiate your processor and make the connections to the RAM here.
   -- P0: proc port map ()

   -- Provide code for the clock divider here. It will generate cnt_clk signal for 
   -- the processor.

end behav;