Thanks to Yan Kiu Chan for providing this. Feb. 6, 2004 Environment Setup: ------------------ You will need to set up some environment variables. On the ugsparcs you should: % source /thesis1/modelsim-5.7f.SUN/CSHRC or on the eecg research machines % source /mentor/modelsim-5.7f/CSHRC and possibly add it to your .cshrc or equivalent to set your path automatically on startup. Invoking, Compiling, Simulating: -------------------------------- Change directory to your project directory, which should include your design files and test bench. Then invoke Modelsim: % vsim Type the following command to create a working directory called "work". This is where Modelsim will compile your design to: % vlib work (GUI: menu File -> New -> Directory) Before simulating your design, you need to compile the source files and test bench. For hierarchical designs, compile the lower level design blocks before the higher level design blocks. To compile, type the following commands: % vlog .v % vlog .v (GUI: menu Compile -> Compile) To simulate your design, type the following command: % vsim For example, if your design has topmost module named "top": % vsim top (GUI: menu Simulate -> Simulate, select the topmost module name from the "Design" tab) If this is a post-synthesis simulation or any Xilinx core macros are instantiated in your Verilog source code, use the following command to simulate your design with the Xilinx Verilog Core Library: vsim -L /thesis1/modelsim-5.7f/modeltech/xilinx_libs/XilinxCoreLib_ver (GUI: add the library to reference in the "Libraries" tab) Viewing Signals: ---------------- To view signals in the design, go to menu View -> Signals. A small window should appear. After you have selected and highlighted the signals you want to appear in the waveform, go to menu Add -> Wave -> Selected Signals. A waveform window should appear. In the main Modelsim command window, type: % run You should now see signals in your waveform.