The process of implementing the Bitmap Mode SVGA example from Xilinx
was not documented and was considerably hard to implement.  A
significant amount of our time was spent on simply implementing this
example as a core to be used in XPS.  Here is a simple how-to guide
using a "Simple Display" example to guide a user on how we created
this project in ISE and how we imported this project as a core into
XPS.  This exercise is extremely useful in learning many aspects of
ISE and XPS, such as how the UCF, MPD, and MHS files are used in
projects.  However, it is not very practical as it creates a hardware
core that generates graphics, instead of using software to generate
the graphics.  This example should be updated with a tutorial on how
to use software to control the display controller.

Creating the display project in ISE

1. Create a new project in ISE and add all of the Verilog files from
the SimpleDisplay.zip file as Verilog sources.  Note that all of these
files except for display.v are from the Bitmap Mode SVGA example from
Xilinx.  The define files are not included as they cause some weird
error in XPS.

2. Add the display.ucf file as a UCF source to the top-level display.v
module of the project.  Open the UCF file and study it.  Note that the
pixel_clock is set to the main system clock pin, reset is set to the
user switch pin, and the memory and SVGA output nets are set to their
appropriate pins.  As the pixel_clock is set as the main system clock,
it runs at 27 MHz.

3. Synthesize, implement, and generate the programming file for the
project.  Upload the bitstream to the multimedia board.  A blue color
is displayed on the top ¾ of the screen, and a brown is displayed on
the bottom ¼.

4. Study the display.v and BM_MODE_SVGA_CTRL.v file to understand how
the project works.  Essentially, an address location in the ZBT memory
corresponds to a certain pixel location on the screen.  The data in
that address location is the RGB value of the pixel.  Refer to the
Mario group report for more information.

Importing the project as a core in XPS

1. Create a new project in XPS

2. With the project open click Tools, Create/Import Peripheral

3. Click Next, then highlight "Import existing peripheral" and click
Next

4. Highlight "To an existing XPS project" and select your project,
click Next

5. Enter the name display and click Next

6. Check HDL source files and click Next

7. Change the drop down box from VHDL to Verilog and highlight "Use an
XST project file".  Select your project file that you created in ISE
and click Next.

8. Click Next, click Next, check No Interrupt and click Next, click
Next, click Next, click Finish

9. Close the project

10. The MPD file in your project/pcores/display/data directory needs
to be changed.  First compare it with the attached display_v2_1_0.mpd
file and then replace it with that file.

11. Open the project, go to Project/Add Edit Cores

12. Add the display core in the Peripherals tab, then click the Ports
tab

13. Add all of the display_0 ports as internal port connections, and
then add them all as external port connections by clicking Make
external with all of them highlighted

14. The port names in the external port connections correspond to the
ports defined in the UCF file.  However, they begin with a display_0
prefix and don’t correspond to our UCF file.  These prefixes must
be removed.  Open the system.mhs file and modify the top section of
the file (these are the external port connections) by removing the
display_0 prefixes.  For example, change:

PORT display_0_VGA_HSYNCH_N = display_0_VGA_HSYNCH_N, DIR = O

To

PORT VGA_HSYNCH_N = display_0_VGA_HSYNCH_N, DIR = O

15. Save the MHS file and the project should now work.  Generate the
Netlist, Bitstream, and download to the multimedia board.