EXTERNAL PORTS
These are the external ports defined in the MHS file.
Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK  indicates Clock ports, (SIGIS = CLK)  INTR  indicates Interrupt ports,(SIGIS = INTR)  RESET  indicates Reset ports, (SIGIS = RST)  BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)
# NAME DIR [LSB:MSB] SIG ATTRIBUTES 0GLB sys_rst_pin I 1 sys_rst_s  RESET  1GLB vid_dec_reset_in I 1 vid_dec_reset_in 2GLB fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin O 0:2 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk 3GLB fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin O 0:2 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn 4GLB fpga_0_DDR_CLK_FB_OUT O 1 ddr_clk_feedback_out_s 5GLB fpga_0_net_gnd_1_pin O 1 net_gnd 6GLB fpga_0_net_gnd_2_pin O 1 net_gnd 7GLB fpga_0_net_gnd_3_pin O 1 net_gnd 8GLB fpga_0_net_gnd_4_pin O 1 net_gnd 9GLB fpga_0_net_gnd_5_pin O 1 net_gnd 10GLB fpga_0_net_gnd_6_pin O 1 net_gnd 11GLB fpga_0_net_gnd_pin O 1 net_gnd 12A fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin IO 0:7 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS 13A fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin IO 0:63 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ 14A fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin O 0:12 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr 15A fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr_pin O 0:1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr 16A fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn_pin O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn 17A fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE_pin O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE 18A fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn_pin O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn 19A fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin O 0:7 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM 20A fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn_pin O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn				# NAME DIR [LSB:MSB] SIG ATTRIBUTES 21A fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn_pin O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn 22B fpga_0_LEDs_4Bit_GPIO_IO_pin IO 0:3 fpga_0_LEDs_4Bit_GPIO_IO 23C fpga_0_RS232_Uart_1_RX_pin I 1 fpga_0_RS232_Uart_1_RX 24C fpga_0_RS232_Uart_1_TX_pin O 1 fpga_0_RS232_Uart_1_TX 25D sys_clk_pin I 1 dcm_clk_s  CLK  26E fpga_0_DDR_CLK_FB I 1 ddr_feedback_s  CLK  27F Scl_decoder IO 1 opb_iic_0_Scl 28F Sda_decoder IO 1 opb_iic_0_Sda 29G LLC_CLOCK I 1 video_capture_0_LLC_CLOCK 30G YCrCb_in I 2:9 video_capture_0_YCrCb_in 31G B O 0:7 video_capture_0_B 32G BLANK_Z O 1 video_capture_0_BLANK_Z 33G COMP_SYNC O 1 video_capture_0_COMP_SYNC 34G G O 0:7 video_capture_0_G 35G H_SYNC_Z O 1 video_capture_0_H_SYNC_Z 36G PIXEL_CLOCK O 1 video_capture_0_PIXEL_CLOCK 37G R O 0:7 video_capture_0_R 38G RESET_VDEC1_Z O 1 video_capture_0_RESET_VDEC1_Z 39G VDEC1_OE_Z O 1 video_capture_0_VDEC1_OE_Z 40G VDEC1_PWRDN_Z O 1 video_capture_0_VDEC1_PWRDN_Z 41G V_SYNC_Z O 1 video_capture_0_V_SYNC_Z