EXTERNAL PORTS
These are the external ports defined in the MHS file.
Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK  indicates Clock ports, (SIGIS = CLK)  INTR  indicates Interrupt ports,(SIGIS = INTR)  RESET  indicates Reset ports, (SIGIS = RST)  BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)
# NAME DIR [LSB:MSB] SIG ATTRIBUTES 0GLB fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk_pin O 0:2 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clk 1GLB fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn_pin O 0:2 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Clkn 2GLB fpga_0_DDR_CLK_FB_OUT O 1 ddr_clk_feedback_out_s 3A fpga_0_Audio_Codec_Bit_Clk_pin I 1 fpga_0_Audio_Codec_Bit_Clk  CLK  4A fpga_0_Audio_Codec_SData_In_pin I 1 fpga_0_Audio_Codec_SData_In 5A fpga_0_Audio_Codec_AC97Reset_n_pin O 1 fpga_0_Audio_Codec_AC97Reset_n 6A fpga_0_Audio_Codec_SData_Out_pin O 1 fpga_0_Audio_Codec_SData_Out 7A fpga_0_Audio_Codec_Sync_pin O 1 fpga_0_Audio_Codec_Sync 8B fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS_pin IO 0:7 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQS 9B fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ_pin IO 0:63 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DQ 10B fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr_pin O 0:12 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_Addr 11B fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr_pin O 0:1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_BankAddr 12B fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn_pin O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CASn 13B fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE_pin O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CKE 14B fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn_pin O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_CSn 15B fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM_pin O 0:7 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_DM 16B fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn_pin O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_RASn 17B fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn_pin O 1 fpga_0_DDR_256MB_32MX64_rank1_row13_col10_cl2_5_DDR_WEn 18C fpga_0_DIPSWs_4Bit_GPIO_IO_pin IO 0:3 fpga_0_DIPSWs_4Bit_GPIO_IO 19D fpga_0_PushButtons_5Bit_GPIO_IO_pin IO 0:4 fpga_0_PushButtons_5Bit_GPIO_IO				# NAME DIR [LSB:MSB] SIG ATTRIBUTES 20E fpga_0_RS232_Uart_1_RX_pin I 1 fpga_0_RS232_Uart_1_RX 21E fpga_0_RS232_Uart_1_TX_pin O 1 fpga_0_RS232_Uart_1_TX 22F fpga_0_SysACE_CompactFlash_SysACE_CLK_pin I 1 fpga_0_SysACE_CompactFlash_SysACE_CLK 23F fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin I 1 fpga_0_SysACE_CompactFlash_SysACE_MPIRQ 24F fpga_0_SysACE_CompactFlash_SysACE_MPD_pin IO 0:15 fpga_0_SysACE_CompactFlash_SysACE_MPD 25F fpga_0_SysACE_CompactFlash_SysACE_CEN_pin O 1 fpga_0_SysACE_CompactFlash_SysACE_CEN 26F fpga_0_SysACE_CompactFlash_SysACE_MPA_pin O 0:6 fpga_0_SysACE_CompactFlash_SysACE_MPA 27F fpga_0_SysACE_CompactFlash_SysACE_OEN_pin O 1 fpga_0_SysACE_CompactFlash_SysACE_OEN 28F fpga_0_SysACE_CompactFlash_SysACE_WEN_pin O 1 fpga_0_SysACE_CompactFlash_SysACE_WEN 29G sys_clk_pin I 1 dcm_clk_s  CLK  30H fpga_0_DDR_CLK_FB I 1 ddr_feedback_s  CLK  31I sys_rst_pin I 1 sys_rst_s  RESET  32J VGA_COMP_SYNCH_N O 1 VGA_COMP_SYNCH_N 33J VGA_HSYNCH O 1 VGA_HSYNCH 34J VGA_OUT_BLANK_N O 1 VGA_OUT_BLANK_N 35J VGA_OUT_BLUE O 0:7 VGA_OUT_BLUE 36J VGA_OUT_GREEN O 0:7 VGA_OUT_GREEN 37J VGA_OUT_PIXEL_CLOCK O 1 VGA_OUT_PIXEL_CLOCK 38J VGA_OUT_RED O 0:7 VGA_OUT_RED 39J VGA_VSYNCH O 1 VGA_VSYNCH