06 Project Status | |||
Project File: | 06.ise | Current State: | Placed and Routed |
Module Name: | top2 |
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No Errors |
Target Device: | xc2vp30-7ff896 |
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2736 Warnings |
Product Version: | ISE 8.2.03i |
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Thu Mar 27 02:19:00 2008 |
06 Partition Summary | |||
No partition information was found. |
Device Utilization Summary | ||||
Logic Utilization | Used | Available | Utilization | Note(s) |
Number of Slice Flip Flops | 409 | 27,392 | 1% | |
Number of 4 input LUTs | 6,533 | 27,392 | 23% | |
Logic Distribution | ||||
Number of occupied Slices | 3,578 | 13,696 | 26% | |
Number of Slices containing only related logic | 3,578 | 3,578 | 100% | |
Number of Slices containing unrelated logic | 0 | 3,578 | 0% | |
Total Number 4 input LUTs | 6,609 | 27,392 | 24% | |
Number used as logic | 6,533 | |||
Number used as a route-thru | 76 | |||
Number of bonded IOBs | 69 | 556 | 12% | |
Number of PPC405s | 0 | 2 | 0% | |
Number of Block RAMs | 32 | 136 | 23% | |
Number of GCLKs | 1 | 16 | 6% | |
Number of GTs | 0 | 8 | 0% | |
Number of GT10s | 0 | 0 | 0% | |
Total equivalent gate count for design | 2,165,836 | |||
Additional JTAG gate count for IOBs | 3,312 |
Performance Summary | |||
Final Timing Score: | 0 | Pinout Data: | Pinout Report |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report |
Timing Constraints: | All Constraints Met |
Detailed Reports | |||||
Report Name | Status | Generated | Errors | Warnings | Infos |
Synthesis Report | Current | Thu Mar 27 01:47:49 2008 | 0 | 2053 Warnings | 4 Infos |
Translation Report | Current | Thu Mar 27 02:10:24 2008 | 0 | 541 Warnings | 0 |
Map Report | Current | Thu Mar 27 02:10:51 2008 | 0 | 141 Warnings | 3 Infos |
Place and Route Report | Current | Thu Mar 27 02:18:42 2008 | 0 | 1 Warning | 0 |
Static Timing Report | Current | Thu Mar 27 02:18:59 2008 | 0 | 0 | 1 Info |
Bitgen Report | Out of Date | Tue Mar 25 00:23:02 2008 | 0 | 141 Warnings | 0 |
Secondary Reports | ||
Report Name | Status | Generated |
Xplorer Report |