Xilinx Design Summary

NES_6502_SYS Partition Summary
No partition information was found.

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	964	27,392	3%
Number of 4 input LUTs	2,147	27,392	7%
Logic Distribution
Number of occupied Slices	1,264	13,696	9%
Number of Slices containing only related logic	1,264	1,264	100%
Number of Slices containing unrelated logic	0	1,264	0%
Total Number 4 input LUTs	2,282	27,392	8%
Number used as logic	2,147
Number used as a route-thru	60
Number used for Dual Port RAMs	74
Number used as Shift registers	1
Number of bonded IOBs	37	556	6%
IOB Flip Flops	3
IOB Master Pads	1
IOB Slave Pads	1
Number of PPC405s	0	2	0%
Number of Block RAMs	53	136	38%
Number of GCLKs	6	16	37%
Number of DCMs	3	8	37%
Number of GTs	0	8	0%
Number of GT10s	0	0	0%
Total equivalent gate count for design	3,526,427
Additional JTAG gate count for IOBs	1,776

Performance Summary
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met