
EXTERNAL PORTS |
These are the external ports defined in the MHS file.
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Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK indicates Clock ports, (SIGIS = CLK) INTR indicates Interrupt ports,(SIGIS = INTR) RESET indicates Reset ports, (SIGIS = RST) BUF or REG Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)
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# |
NAME |
DIR |
[LSB:MSB] |
SIG |
ATTRIBUTES |
0GLB
|
sys_rst_pin |
I |
1 |
sys_rst_s |
RESET |
1A
|
fpga_0_RS232_Uart_1_RX_pin |
I |
1 |
fpga_0_RS232_Uart_1_RX |
|
2A
|
fpga_0_RS232_Uart_1_TX_pin |
O |
1 |
fpga_0_RS232_Uart_1_TX |
|
3B
|
fpga_0_Audio_Codec_Bit_Clk_pin |
I |
1 |
fpga_0_Audio_Codec_Bit_Clk |
|
4B
|
fpga_0_Audio_Codec_SData_In_pin |
I |
1 |
fpga_0_Audio_Codec_SData_In |
|
5B
|
fpga_0_Audio_Codec_AC97Reset_n_pin |
O |
1 |
fpga_0_Audio_Codec_AC97Reset_n |
|
6B
|
fpga_0_Audio_Codec_SData_Out_pin |
O |
1 |
fpga_0_Audio_Codec_SData_Out |
|
7B
|
fpga_0_Audio_Codec_Sync_pin |
O |
1 |
fpga_0_Audio_Codec_Sync |
|
8C
|
sys_clk_pin |
I |
1 |
dcm_clk_s |
CLK |
9C
|
fpga_0_net_gnd_1_pin |
O |
1 |
net_gnd |
|
10C
|
fpga_0_net_gnd_2_pin |
O |
1 |
net_gnd |
|
11C
|
fpga_0_net_gnd_3_pin |
O |
1 |
net_gnd |
|
12C
|
fpga_0_net_gnd_4_pin |
O |
1 |
net_gnd |
|
13C
|
fpga_0_net_gnd_5_pin |
O |
1 |
net_gnd |
|
14C
|
fpga_0_net_gnd_6_pin |
O |
1 |
net_gnd |
|
15C
|
fpga_0_net_gnd_pin |
O |
1 |
net_gnd |
|
|