| EXTERNAL PORTS |
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These are the external ports defined in the MHS file.
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Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLK indicates Clock ports, (SIGIS = CLK)
INTR indicates Interrupt ports,(SIGIS = INTR)
RESET indicates Reset ports, (SIGIS = RST)
BUF or REG Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)
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| # |
NAME |
DIR |
[LSB:MSB] |
SIG |
ATTRIBUTES |
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0GLB
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sys_rst_pin |
I |
1 |
sys_rst_s |
RESET |
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1A
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VGA_COMP_SYNCH_N |
O |
1 |
display_0_VGA_COMP_SYNCH_N |
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2A
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VGA_HSYNCH |
O |
1 |
display_0_VGA_HSYNCH_N |
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3A
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VGA_OUT_BLANK_N |
O |
1 |
display_0_VGA_OUT_BLANK_N |
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4A
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VGA_OUT_BLUE |
O |
0:7 |
display_0_VGA_OUT_BLUE_P |
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5A
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VGA_OUT_GREEN |
O |
0:7 |
display_0_VGA_OUT_GREEN_P |
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6A
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VGA_OUT_PIXEL_CLOCK |
O |
1 |
display_0_VGA_OUT_PIXEL_CLOCK_P |
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7A
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VGA_OUT_RED |
O |
0:7 |
display_0_VGA_OUT_RED_P |
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8A
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VGA_VSYNCH |
O |
1 |
display_0_VGA_VSYNCH_N |
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9B
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fpga_0_RS232_Uart_1_RX_pin |
I |
1 |
fpga_0_RS232_Uart_1_RX |
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| # |
NAME |
DIR |
[LSB:MSB] |
SIG |
ATTRIBUTES |
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10B
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fpga_0_RS232_Uart_1_TX_pin |
O |
1 |
fpga_0_RS232_Uart_1_TX |
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11C
|
sys_clk_pin |
I |
1 |
dcm_clk_s |
CLK |
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12C
|
fpga_0_net_gnd_1_pin |
O |
1 |
net_gnd |
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13C
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fpga_0_net_gnd_2_pin |
O |
1 |
net_gnd |
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14C
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fpga_0_net_gnd_3_pin |
O |
1 |
net_gnd |
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15C
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fpga_0_net_gnd_4_pin |
O |
1 |
net_gnd |
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16C
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fpga_0_net_gnd_5_pin |
O |
1 |
net_gnd |
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17C
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fpga_0_net_gnd_6_pin |
O |
1 |
net_gnd |
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18C
|
fpga_0_net_gnd_pin |
O |
1 |
net_gnd |
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