# |
NAME |
DIR |
[LSB:MSB] |
SIG |
ATTRIBUTES |
0GLB
|
vid_dec_reset_in |
I |
1 |
vid_dec_reset_in |
|
1A
|
fpga_0_DDR_SDRAM_DDR_DQ |
IO |
63:0 |
fpga_0_DDR_SDRAM_DDR_DQ |
|
2A
|
fpga_0_DDR_SDRAM_DDR_DQS |
IO |
7:0 |
fpga_0_DDR_SDRAM_DDR_DQS |
|
3A
|
fpga_0_DDR_SDRAM_DDR_Addr_pin |
O |
12:0 |
fpga_0_DDR_SDRAM_DDR_Addr |
|
4A
|
fpga_0_DDR_SDRAM_DDR_BankAddr_pin |
O |
1:0 |
fpga_0_DDR_SDRAM_DDR_BankAddr |
|
5A
|
fpga_0_DDR_SDRAM_DDR_CAS_n_pin |
O |
1 |
fpga_0_DDR_SDRAM_DDR_CAS_n |
|
6A
|
fpga_0_DDR_SDRAM_DDR_CE_pin |
O |
1:0 |
fpga_0_DDR_SDRAM_DDR_CE |
|
7A
|
fpga_0_DDR_SDRAM_DDR_CS_n_pin |
O |
1:0 |
fpga_0_DDR_SDRAM_DDR_CS_n |
|
8A
|
fpga_0_DDR_SDRAM_DDR_Clk_n_pin |
O |
2:0 |
fpga_0_DDR_SDRAM_DDR_Clk_n |
|
9A
|
fpga_0_DDR_SDRAM_DDR_Clk_pin |
O |
2:0 |
fpga_0_DDR_SDRAM_DDR_Clk |
|
10A
|
fpga_0_DDR_SDRAM_DDR_DM_pin |
O |
7:0 |
fpga_0_DDR_SDRAM_DDR_DM |
|
11A
|
fpga_0_DDR_SDRAM_DDR_RAS_n_pin |
O |
1 |
fpga_0_DDR_SDRAM_DDR_RAS_n |
|
12A
|
fpga_0_DDR_SDRAM_DDR_WE_n_pin |
O |
1 |
fpga_0_DDR_SDRAM_DDR_WE_n |
|
13B
|
IIC_Scl_pin |
IO |
1 |
IIC_Scl |
|
14B
|
IIC_Sda_pin |
IO |
1 |
IIC_Sda |
|
15C
|
sys_clk_pin |
I |
1 |
dcm_clk_s |
CLK |
16C
|
fpga_0_net_gnd_1_pin |
O |
1 |
net_gnd |
|
17C
|
fpga_0_net_gnd_2_pin |
O |
1 |
net_gnd |
|
18C
|
fpga_0_net_gnd_3_pin |
O |
1 |
net_gnd |
|
19C
|
fpga_0_net_gnd_4_pin |
O |
1 |
net_gnd |
|