EXTERNAL PORTS
These are the external ports defined in the MHS file.
Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK  indicates Clock ports, (SIGIS = CLK)  INTR  indicates Interrupt ports,(SIGIS = INTR)  RESET  indicates Reset ports, (SIGIS = RST)  BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)
# NAME DIR [LSB:MSB] SIG ATTRIBUTES sys_clk_pin I 1 dcm_clk_s  CLK  sys_rst_pin I 1 sys_rst_s  RESET  VGA_VSYNCH_pin O 1 VGA_VSYNCH VGA_HSYNCH_pin O 1 VGA_HSYNCH VGA_OUT_BLANK_Z_pin O 1 VGA_OUT_BLANK_Z VGA_COMP_SYNCH_pin O 1 VGA_COMP_SYNCH VGA_PIXEL_CLOCK_pin O 1 VGA_PIXEL_CLOCK VGA_OUT_RED_pin O 5:0 VGA_OUT_RED VGA_OUT_GREEN_pin O 5:0 VGA_OUT_GREEN VGA_OUT_BLUE_pin O 5:0 VGA_OUT_BLUE fpga_0_RS232_Uart_1_RX_pin I 1 fpga_0_RS232_Uart_1_RX fpga_0_RS232_Uart_1_TX_pin O 1 fpga_0_RS232_Uart_1_TX fpga_0_DDR_SDRAM_DDR_Clk_pin O 2:0 fpga_0_DDR_SDRAM_DDR_Clk fpga_0_DDR_SDRAM_DDR_Clk_n_pin O 2:0 fpga_0_DDR_SDRAM_DDR_Clk_n fpga_0_DDR_SDRAM_DDR_Addr_pin O 12:0 fpga_0_DDR_SDRAM_DDR_Addr fpga_0_DDR_SDRAM_DDR_BankAddr_pin O 1:0 fpga_0_DDR_SDRAM_DDR_BankAddr fpga_0_DDR_SDRAM_DDR_CAS_n_pin O 1 fpga_0_DDR_SDRAM_DDR_CAS_n fpga_0_DDR_SDRAM_DDR_CE_pin O 1:0 fpga_0_DDR_SDRAM_DDR_CE fpga_0_DDR_SDRAM_DDR_CS_n_pin O 1:0 fpga_0_DDR_SDRAM_DDR_CS_n fpga_0_DDR_SDRAM_DDR_RAS_n_pin O 1 fpga_0_DDR_SDRAM_DDR_RAS_n fpga_0_DDR_SDRAM_DDR_WE_n_pin O 1 fpga_0_DDR_SDRAM_DDR_WE_n				# NAME DIR [LSB:MSB] SIG ATTRIBUTES fpga_0_DDR_SDRAM_DDR_DM_pin O 7:0 fpga_0_DDR_SDRAM_DDR_DM fpga_0_DDR_SDRAM_DDR_DQS IO 7:0 fpga_0_DDR_SDRAM_DDR_DQS fpga_0_DDR_SDRAM_DDR_DQ IO 63:0 fpga_0_DDR_SDRAM_DDR_DQ ac97_sdata_out_pin O 1 ac97_sdata_out ac97_sdata_in_pin I 1 ac97_sdata_in ac97_synch_pin O 1 ac97_synch ac97_bit_clock_pin I 1 ac97_bit_clock audio_reset_b_pin O 1 audio_reset_b fpga_0_net_gnd_pin O 1 net_gnd fpga_0_net_gnd_1_pin O 1 net_gnd fpga_0_net_gnd_2_pin O 1 net_gnd fpga_0_net_gnd_3_pin O 1 net_gnd fpga_0_net_gnd_4_pin O 1 net_gnd fpga_0_net_gnd_5_pin O 1 net_gnd fpga_0_net_gnd_6_pin O 1 net_gnd vid_dec_reset_in I 1 vid_dec_reset_in adc_data_reader_0_gpio_channel_pin I 1:0 adc_data_reader_0_gpio_channel adc_data_reader_0_gpio_data_pin I 1 adc_data_reader_0_gpio_data adc_data_reader_0_gpio_lat_pin I 1 adc_data_reader_0_gpio_lat adc_data_reader_0_gpio_clk_pin I 1 adc_data_reader_0_gpio_clk  CLK