# |
NAME |
DIR |
[LSB:MSB] |
SIG |
ATTRIBUTES |
|
fpga_0_RS232_Uart_1_RX_pin |
I |
1 |
fpga_0_RS232_Uart_1_RX |
|
|
fpga_0_RS232_Uart_1_TX_pin |
O |
1 |
fpga_0_RS232_Uart_1_TX |
|
|
fpga_0_DDR_SDRAM_DDR_Clk_pin |
O |
2:0 |
fpga_0_DDR_SDRAM_DDR_Clk |
|
|
fpga_0_DDR_SDRAM_DDR_Clk_n_pin |
O |
2:0 |
fpga_0_DDR_SDRAM_DDR_Clk_n |
|
|
fpga_0_DDR_SDRAM_DDR_Addr_pin |
O |
12:0 |
fpga_0_DDR_SDRAM_DDR_Addr |
|
|
fpga_0_DDR_SDRAM_DDR_BankAddr_pin |
O |
1:0 |
fpga_0_DDR_SDRAM_DDR_BankAddr |
|
|
fpga_0_DDR_SDRAM_DDR_CAS_n_pin |
O |
1 |
fpga_0_DDR_SDRAM_DDR_CAS_n |
|
|
fpga_0_DDR_SDRAM_DDR_CE_pin |
O |
1 |
fpga_0_DDR_SDRAM_DDR_CE |
|
|
fpga_0_DDR_SDRAM_DDR_CS_n_pin |
O |
1 |
fpga_0_DDR_SDRAM_DDR_CS_n |
|
|
fpga_0_DDR_SDRAM_DDR_RAS_n_pin |
O |
1 |
fpga_0_DDR_SDRAM_DDR_RAS_n |
|
|
fpga_0_DDR_SDRAM_DDR_WE_n_pin |
O |
1 |
fpga_0_DDR_SDRAM_DDR_WE_n |
|
|
fpga_0_DDR_SDRAM_DDR_DM_pin |
O |
7:0 |
fpga_0_DDR_SDRAM_DDR_DM |
|
|
fpga_0_DDR_SDRAM_DDR_DQS |
IO |
7:0 |
fpga_0_DDR_SDRAM_DDR_DQS |
|
|
fpga_0_DDR_SDRAM_DDR_DQ |
IO |
63:0 |
fpga_0_DDR_SDRAM_DDR_DQ |
|
|
fpga_0_net_gnd_pin |
O |
1 |
net_gnd |
|
|
fpga_0_net_gnd_1_pin |
O |
1 |
net_gnd |
|
|
fpga_0_net_gnd_2_pin |
O |
1 |
net_gnd |
|
|
fpga_0_net_gnd_3_pin |
O |
1 |
net_gnd |
|
|
fpga_0_net_gnd_4_pin |
O |
1 |
net_gnd |
|