EXTERNAL PORTS
These are the external ports defined in the MHS file.
Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK  indicates Clock ports, (SIGIS = CLK)  INTR  indicates Interrupt ports,(SIGIS = INTR)  RESET  indicates Reset ports, (SIGIS = RST)  BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)
# NAME DIR [LSB:MSB] SIG ATTRIBUTES fpga_0_RS232_Uart_1_RX_pin I 1 fpga_0_RS232_Uart_1_RX fpga_0_RS232_Uart_1_TX_pin O 1 fpga_0_RS232_Uart_1_TX fpga_0_DDR_SDRAM_DDR_Clk_pin O 2:0 fpga_0_DDR_SDRAM_DDR_Clk fpga_0_DDR_SDRAM_DDR_Clk_n_pin O 2:0 fpga_0_DDR_SDRAM_DDR_Clk_n fpga_0_DDR_SDRAM_DDR_Addr_pin O 12:0 fpga_0_DDR_SDRAM_DDR_Addr fpga_0_DDR_SDRAM_DDR_BankAddr_pin O 1:0 fpga_0_DDR_SDRAM_DDR_BankAddr fpga_0_DDR_SDRAM_DDR_CAS_n_pin O 1 fpga_0_DDR_SDRAM_DDR_CAS_n fpga_0_DDR_SDRAM_DDR_CE_pin O 1 fpga_0_DDR_SDRAM_DDR_CE fpga_0_DDR_SDRAM_DDR_CS_n_pin O 1 fpga_0_DDR_SDRAM_DDR_CS_n fpga_0_DDR_SDRAM_DDR_RAS_n_pin O 1 fpga_0_DDR_SDRAM_DDR_RAS_n fpga_0_DDR_SDRAM_DDR_WE_n_pin O 1 fpga_0_DDR_SDRAM_DDR_WE_n fpga_0_DDR_SDRAM_DDR_DM_pin O 7:0 fpga_0_DDR_SDRAM_DDR_DM fpga_0_DDR_SDRAM_DDR_DQS IO 7:0 fpga_0_DDR_SDRAM_DDR_DQS fpga_0_DDR_SDRAM_DDR_DQ IO 63:0 fpga_0_DDR_SDRAM_DDR_DQ fpga_0_net_gnd_pin O 1 net_gnd fpga_0_net_gnd_1_pin O 1 net_gnd fpga_0_net_gnd_2_pin O 1 net_gnd fpga_0_net_gnd_3_pin O 1 net_gnd fpga_0_net_gnd_4_pin O 1 net_gnd				# NAME DIR [LSB:MSB] SIG ATTRIBUTES fpga_0_net_gnd_5_pin O 1 net_gnd fpga_0_net_gnd_6_pin O 1 net_gnd sys_clk_pin I 1 dcm_clk_s  CLK  sys_rst_pin I 1 sys_rst_s  RESET  VGA_OUT_BLUE O 5:0 VGA_OUT_BLUE VGA_OUT_RED O 5:0 VGA_OUT_RED VGA_OUT_PIXEL_CLOCK O 1 VGA_OUT_PIXEL_CLOCK xps_tft_0_TFT_DPS O 1 xps_tft_0_TFT_DPS xps_tft_0_TFT_DE O 1 xps_tft_0_TFT_DE VGA_VSYNCH O 1 VGA_VSYNCH VGA_HSYNCH O 1 VGA_HSYNCH VGA_OUT_GREEN O 5:0 VGA_OUT_GREEN Scl_decoder IO 1 xps_iic_0_Scl Sda_decoder IO 1 xps_iic_0_Sda VDEC1_PWRDN_Z O 1 ip_to_mem_0_VDEC1_PWRDN_Z VDEC1_OE_Z O 1 ip_to_mem_0_VDEC1_OE_Z RESET_VDEC1_Z O 1 ip_to_mem_0_RESET_VDEC1_Z LLC_CLOCK I 1 ip_to_mem_0_LLC_CLOCK YCrCb_in I 9:2 ip_to_mem_0_YCrCb_in