| EXTERNAL PORTS |
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These are the external ports defined in the MHS file.
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Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLK indicates Clock ports, (SIGIS = CLK)
INTR indicates Interrupt ports,(SIGIS = INTR)
RESET indicates Reset ports, (SIGIS = RST)
BUF or REG Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)
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| # |
NAME |
DIR |
[LSB:MSB] |
SIG |
ATTRIBUTES |
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sys_clk_pin |
I |
1 |
dcm_clk_s |
CLK |
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sys_rst_pin |
I |
1 |
sys_rst_s |
RESET |
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LLC_CLOCK_pin |
I |
1 |
LLC_CLOCK |
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YCrCb_in_pin |
I |
9:2 |
YCrCb_in |
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IIC_Scl_pin |
IO |
1 |
IIC_Scl |
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IIC_Sda_pin |
IO |
1 |
IIC_Sda |
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VGA_VSYNCH_pin |
O |
1 |
VGA_VSYNCH |
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VGA_HSYNCH_pin |
O |
1 |
VGA_HSYNCH |
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VGA_OUT_BLANK_Z_pin |
O |
1 |
VGA_OUT_BLANK_Z |
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VGA_COMP_SYNCH_pin |
O |
1 |
VGA_COMP_SYNCH |
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VGA_PIXEL_CLOCK_pin |
O |
1 |
VGA_PIXEL_CLOCK |
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VGA_OUT_RED_pin |
O |
5:0 |
VGA_OUT_RED |
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VGA_OUT_GREEN_pin |
O |
5:0 |
VGA_OUT_GREEN |
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VGA_OUT_BLUE_pin |
O |
5:0 |
VGA_OUT_BLUE |
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fpga_0_RS232_Uart_1_RX_pin |
I |
1 |
fpga_0_RS232_Uart_1_RX |
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fpga_0_RS232_Uart_1_TX_pin |
O |
1 |
fpga_0_RS232_Uart_1_TX |
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LED_pin |
O |
3:0 |
LED |
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DIP_SW_pin |
I |
3:0 |
DIP_SW |
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fpga_0_DDR_SDRAM_DDR_Clk_pin |
O |
2:0 |
fpga_0_DDR_SDRAM_DDR_Clk |
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fpga_0_DDR_SDRAM_DDR_Clk_n_pin |
O |
2:0 |
fpga_0_DDR_SDRAM_DDR_Clk_n |
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fpga_0_DDR_SDRAM_DDR_Addr_pin |
O |
12:0 |
fpga_0_DDR_SDRAM_DDR_Addr |
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| # |
NAME |
DIR |
[LSB:MSB] |
SIG |
ATTRIBUTES |
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fpga_0_DDR_SDRAM_DDR_BankAddr_pin |
O |
1:0 |
fpga_0_DDR_SDRAM_DDR_BankAddr |
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fpga_0_DDR_SDRAM_DDR_CAS_n_pin |
O |
1 |
fpga_0_DDR_SDRAM_DDR_CAS_n |
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fpga_0_DDR_SDRAM_DDR_CE_pin |
O |
1:0 |
fpga_0_DDR_SDRAM_DDR_CE |
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fpga_0_DDR_SDRAM_DDR_CS_n_pin |
O |
1:0 |
fpga_0_DDR_SDRAM_DDR_CS_n |
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fpga_0_DDR_SDRAM_DDR_RAS_n_pin |
O |
1 |
fpga_0_DDR_SDRAM_DDR_RAS_n |
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fpga_0_DDR_SDRAM_DDR_WE_n_pin |
O |
1 |
fpga_0_DDR_SDRAM_DDR_WE_n |
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fpga_0_DDR_SDRAM_DDR_DM_pin |
O |
7:0 |
fpga_0_DDR_SDRAM_DDR_DM |
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fpga_0_DDR_SDRAM_DDR_DQS |
IO |
7:0 |
fpga_0_DDR_SDRAM_DDR_DQS |
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fpga_0_DDR_SDRAM_DDR_DQ |
IO |
63:0 |
fpga_0_DDR_SDRAM_DDR_DQ |
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video_to_ram_0_i_DBG_new_line_pin |
I |
1 |
video_to_ram_0_i_DBG_new_line |
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fpga_0_net_gnd_pin |
O |
1 |
net_gnd |
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fpga_0_net_gnd_1_pin |
O |
1 |
net_gnd |
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fpga_0_net_gnd_2_pin |
O |
1 |
net_gnd |
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fpga_0_net_gnd_3_pin |
O |
1 |
net_gnd |
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fpga_0_net_gnd_4_pin |
O |
1 |
net_gnd |
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fpga_0_net_gnd_5_pin |
O |
1 |
net_gnd |
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fpga_0_net_gnd_6_pin |
O |
1 |
net_gnd |
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vid_dec_reset_in |
I |
1 |
vid_dec_reset_in |
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xps_ps2_0_PS2_1_DATA |
IO |
1 |
xps_ps2_0_PS2_1_DATA |
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xps_ps2_0_PS2_1_CLK |
IO |
1 |
xps_ps2_0_PS2_1_CLK |
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