EXTERNAL PORTS
These are the external ports defined in the MHS file.
Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLK  indicates Clock ports, (SIGIS = CLK) 
INTR  indicates Interrupt ports,(SIGIS = INTR) 
RESET  indicates Reset ports, (SIGIS = RST) 
BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG) 
# NAME DIR [LSB:MSB] SIG ATTRIBUTES
sys_clk_pin I 1 dcm_clk_s  CLK 
sys_rst_pin I 1 sys_rst_s  RESET 
LLC_CLOCK_pin I 1 LLC_CLOCK
YCrCb_in_pin I 9:2 YCrCb_in
IIC_Scl_pin IO 1 IIC_Scl
IIC_Sda_pin IO 1 IIC_Sda
VGA_VSYNCH_pin O 1 VGA_VSYNCH
VGA_HSYNCH_pin O 1 VGA_HSYNCH
VGA_OUT_BLANK_Z_pin O 1 VGA_OUT_BLANK_Z
VGA_COMP_SYNCH_pin O 1 VGA_COMP_SYNCH
VGA_PIXEL_CLOCK_pin O 1 VGA_PIXEL_CLOCK
VGA_OUT_RED_pin O 5:0 VGA_OUT_RED
VGA_OUT_GREEN_pin O 5:0 VGA_OUT_GREEN
VGA_OUT_BLUE_pin O 5:0 VGA_OUT_BLUE
fpga_0_RS232_Uart_1_RX_pin I 1 fpga_0_RS232_Uart_1_RX
fpga_0_RS232_Uart_1_TX_pin O 1 fpga_0_RS232_Uart_1_TX
LED_pin O 3:0 LED
DIP_SW_pin I 3:0 DIP_SW
fpga_0_DDR_SDRAM_DDR_Clk_pin O 2:0 fpga_0_DDR_SDRAM_DDR_Clk
fpga_0_DDR_SDRAM_DDR_Clk_n_pin O 2:0 fpga_0_DDR_SDRAM_DDR_Clk_n
fpga_0_DDR_SDRAM_DDR_Addr_pin O 12:0 fpga_0_DDR_SDRAM_DDR_Addr
 
# NAME DIR [LSB:MSB] SIG ATTRIBUTES
fpga_0_DDR_SDRAM_DDR_BankAddr_pin O 1:0 fpga_0_DDR_SDRAM_DDR_BankAddr
fpga_0_DDR_SDRAM_DDR_CAS_n_pin O 1 fpga_0_DDR_SDRAM_DDR_CAS_n
fpga_0_DDR_SDRAM_DDR_CE_pin O 1:0 fpga_0_DDR_SDRAM_DDR_CE
fpga_0_DDR_SDRAM_DDR_CS_n_pin O 1:0 fpga_0_DDR_SDRAM_DDR_CS_n
fpga_0_DDR_SDRAM_DDR_RAS_n_pin O 1 fpga_0_DDR_SDRAM_DDR_RAS_n
fpga_0_DDR_SDRAM_DDR_WE_n_pin O 1 fpga_0_DDR_SDRAM_DDR_WE_n
fpga_0_DDR_SDRAM_DDR_DM_pin O 7:0 fpga_0_DDR_SDRAM_DDR_DM
fpga_0_DDR_SDRAM_DDR_DQS IO 7:0 fpga_0_DDR_SDRAM_DDR_DQS
fpga_0_DDR_SDRAM_DDR_DQ IO 63:0 fpga_0_DDR_SDRAM_DDR_DQ
video_to_ram_0_i_DBG_new_line_pin I 1 video_to_ram_0_i_DBG_new_line
fpga_0_net_gnd_pin O 1 net_gnd
fpga_0_net_gnd_1_pin O 1 net_gnd
fpga_0_net_gnd_2_pin O 1 net_gnd
fpga_0_net_gnd_3_pin O 1 net_gnd
fpga_0_net_gnd_4_pin O 1 net_gnd
fpga_0_net_gnd_5_pin O 1 net_gnd
fpga_0_net_gnd_6_pin O 1 net_gnd
vid_dec_reset_in I 1 vid_dec_reset_in
xps_ps2_0_PS2_1_DATA IO 1 xps_ps2_0_PS2_1_DATA
xps_ps2_0_PS2_1_CLK IO 1 xps_ps2_0_PS2_1_CLK