EXTERNAL PORTS
These are the external ports defined in the MHS file.
Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK  indicates Clock ports, (SIGIS = CLK)  INTR  indicates Interrupt ports,(SIGIS = INTR)  RESET  indicates Reset ports, (SIGIS = RST)  BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)
# NAME DIR [LSB:MSB] SIG ATTRIBUTES 0GLB comparison_module_0_CLOCK_25_pin I 1 comparison_module_0_CLOCK_25 1A fpga_0_DDR_SDRAM_DDR_DQ IO 63:0 fpga_0_DDR_SDRAM_DDR_DQ 2A fpga_0_DDR_SDRAM_DDR_DQS IO 7:0 fpga_0_DDR_SDRAM_DDR_DQS 3A fpga_0_DDR_SDRAM_DDR_Addr_pin O 12:0 fpga_0_DDR_SDRAM_DDR_Addr 4A fpga_0_DDR_SDRAM_DDR_BankAddr_pin O 1:0 fpga_0_DDR_SDRAM_DDR_BankAddr 5A fpga_0_DDR_SDRAM_DDR_CAS_n_pin O 1 fpga_0_DDR_SDRAM_DDR_CAS_n 6A fpga_0_DDR_SDRAM_DDR_CE_pin O 1:0 fpga_0_DDR_SDRAM_DDR_CE 7A fpga_0_DDR_SDRAM_DDR_CS_n_pin O 1:0 fpga_0_DDR_SDRAM_DDR_CS_n 8A fpga_0_DDR_SDRAM_DDR_Clk_n_pin O 2:0 fpga_0_DDR_SDRAM_DDR_Clk_n 9A fpga_0_DDR_SDRAM_DDR_Clk_pin O 2:0 fpga_0_DDR_SDRAM_DDR_Clk 10A fpga_0_DDR_SDRAM_DDR_DM_pin O 7:0 fpga_0_DDR_SDRAM_DDR_DM 11A fpga_0_DDR_SDRAM_DDR_RAS_n_pin O 1 fpga_0_DDR_SDRAM_DDR_RAS_n 12A fpga_0_DDR_SDRAM_DDR_WE_n_pin O 1 fpga_0_DDR_SDRAM_DDR_WE_n 13B IIC_Scl_pin IO 1 IIC_Scl 14B IIC_Sda_pin IO 1 IIC_Sda 15C fpga_0_RS232_Uart_1_RX_pin I 1 fpga_0_RS232_Uart_1_RX 16C fpga_0_RS232_Uart_1_TX_pin O 1 fpga_0_RS232_Uart_1_TX 17D sys_clk_pin I 1 dcm_clk_s  CLK  18D fpga_0_net_gnd_1_pin O 1 net_gnd 19D fpga_0_net_gnd_2_pin O 1 net_gnd 20D fpga_0_net_gnd_3_pin O 1 net_gnd 21D fpga_0_net_gnd_4_pin O 1 net_gnd				# NAME DIR [LSB:MSB] SIG ATTRIBUTES 22D fpga_0_net_gnd_5_pin O 1 net_gnd 23D fpga_0_net_gnd_6_pin O 1 net_gnd 24D fpga_0_net_gnd_pin O 1 net_gnd 25E comparison_module_0_SW_0_pin I 1 comparison_module_0_SW_0 26E comparison_module_0_SW_1_pin I 1 comparison_module_0_SW_1 27E comparison_module_0_SW_2_pin I 1 comparison_module_0_SW_2 28E comparison_module_0_SW_3_pin I 1 comparison_module_0_SW_3 29E comparison_module_0_LED_0_pin O 1 comparison_module_0_LED_0 30E comparison_module_0_LED_1_pin O 1 comparison_module_0_LED_1 31E comparison_module_0_LED_2_pin O 1 comparison_module_0_LED_2 32E comparison_module_0_LED_3_pin O 1 comparison_module_0_LED_3 33E comparison_module_0_VGA_COMP_SYNCH_pin O 1 comparison_module_0_VGA_COMP_SYNCH 34E comparison_module_0_VGA_HSYNCH_pin O 1 comparison_module_0_VGA_HSYNCH 35E comparison_module_0_VGA_OUT_BLANK_Z_pin O 1 comparison_module_0_VGA_OUT_BLANK_Z 36E comparison_module_0_VGA_OUT_BLUE_pin O 0:7 comparison_module_0_VGA_OUT_BLUE 37E comparison_module_0_VGA_OUT_GREEN_pin O 0:7 comparison_module_0_VGA_OUT_GREEN 38E comparison_module_0_VGA_OUT_PIXEL_CLOCK_pin O 1 comparison_module_0_VGA_OUT_PIXEL_CLOCK 39E comparison_module_0_VGA_OUT_RED_pin O 0:7 comparison_module_0_VGA_OUT_RED 40E comparison_module_0_VGA_VSYNCH_pin O 1 comparison_module_0_VGA_VSYNCH 41F sys_rst_pin I 1 sys_rst_s  RESET  42G LLC_CLOCK_pin I 1 LLC_CLOCK 43G YCrCb_in_pin I 9:2 YCrCb_in