Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
date_generatedTue Mar 17 16:54:10 2015 product_versionVivado v2014.1 (64-bit)
build_version881834 os_platformWIN64
registration_id tool_flowVivado
betaFALSE route_designTRUE
target_familyartix7 target_devicexc7a100t
target_packagecsg324 target_speed-1
random_idd2850dd1c4305287bf72c62974ed020c project_idda8efb571e6c402392de43d20959d2e4
project_iteration1

user_environment
os_nameMicrosoft Windows 8 or later , 64-bit os_releasemajor release (build 9200)
cpu_nameIntel(R) Core(TM) i7-4700MQ CPU @ 2.40GHz cpu_speed2394 MHz
total_processors1 system_ram8.000 GB

vivado_usage
project_data
srcsetcount=0 constraintsetcount=0 designmode=GateLvl prproject=false
reconfigpartitioncount=0 reconfigmodulecount=0 hdproject=false partitioncount=0
synthesisstrategy=[unknown] implstrategy=Vivado Implementation Defaults currentsynthesisrun=[unknown] currentimplrun=impl_1
totalsynthesisruns=0 totalimplruns=1

unisim_transformation
pre_unisim_transformation
and2b1l=1 bscane2=1 bufg=4 carry4=155
dsp48e1=5 fdce=210 fdpe=5 fdre=6508
fdse=61 gnd=136 ibuf=4 lut1=59
lut2=673 lut3=761 lut4=487 lut5=506
lut6=1124 lut6_2=80 mmcme2_adv=1 muxf7=120
muxf8=1 obuf=1 ram32m=16 ram32x1d=32
ramb36e1=33 srl16e=119 srlc16e=7 srlc32e=1
vcc=22
post_unisim_transformation
and2b1l=1 bscane2=1 bufg=4 carry4=155
dsp48e1=5 fdce=210 fdpe=5 fdre=6508
fdse=61 gnd=136 ibuf=4 lut1=59
lut2=673 lut3=761 lut4=487 lut5=586
lut6=1204 mmcme2_adv=1 muxf7=120 muxf8=1
obuf=1 ramb36e1=33 ramd32=160 rams32=32
srl16e=119 srlc16e=7 srlc32e=1 vcc=22

placer
usage
lut=3043 ff=2435 bram36=33 bram18=0
ctrls=107 dsp=5 iob=5 bufg=0
global_clocks=4 pll=0 bufr=0 nets=7678
movable_instances=6466 pins=45976 bogomips=0 effort=2
threads=2 placer_timing_driven=1 timing_constraints_exist=1 placer_runtime=91.558000

power_opt_design
usage
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=2435 srls_augmented=0
srls_newly_gated=0 srls_total=127 bram_ports_augmented=0 bram_ports_newly_gated=0
bram_ports_total=66 flow_state=default
command_line_options_spo
-clocks=default::[not_specified] -include_cells=default::[not_specified] -exclude_cells=default::[not_specified] -cell_types=default::all

ip_statistics
IP_Integrator/1
iptotal=1 x_ipvendor=xilinx.com x_iplanguage=VERILOG numblks=20
numreposblks=14 numnonxlnxblks=0 numhierblks=6 maxhierdepth=1
da_axi4_cnt=2 da_board_cnt=4 da_mb_cnt=1
MDM/1
iptotal=1 x_ipproduct=Vivado 2014.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=mdm x_ipversion=3.1 x_ipcorerevision=0 x_iplanguage=VERILOG
c_family=artix7 c_jtag_chain=2 c_use_bscan=0 c_use_config_reset=0
c_interconnect=2 c_mb_dbg_ports=1 c_use_uart=0 c_dbg_reg_access=0
c_dbg_mem_access=0 c_use_cross_trigger=0 c_s_axi_addr_width=32 c_s_axi_data_width=32
c_s_axi_aclk_freq_hz=100000000 c_m_axi_addr_width=32 c_m_axi_data_width=32 c_m_axi_thread_id_width=1
c_data_size=32
MicroBlaze/1
iptotal=1 x_ipproduct=Vivado 2014.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=microblaze x_ipversion=9.3 x_ipcorerevision=0 x_iplanguage=VERILOG
c_sco=0 c_freq=100000000 c_use_config_reset=0 c_fault_tolerant=0
c_ecc_use_ce_exception=0 c_lockstep_slave=0 c_endianness=1 c_family=artix7
c_data_size=32 c_instance=design_1_microblaze_0_0 c_avoid_primitives=0 c_area_optimized=0
c_optimization=0 c_interconnect=2 c_base_vectors=0x00000000 c_m_axi_dp_thread_id_width=1
c_m_axi_dp_data_width=32 c_m_axi_dp_addr_width=32 c_m_axi_dp_exclusive_access=0 c_m_axi_d_bus_exception=0
c_m_axi_ip_thread_id_width=1 c_m_axi_ip_data_width=32 c_m_axi_ip_addr_width=32 c_m_axi_i_bus_exception=0
c_d_lmb=1 c_d_axi=1 c_i_lmb=1 c_i_axi=0
c_use_msr_instr=0 c_use_pcmp_instr=0 c_use_barrel=1 c_use_div=1
c_use_hw_mul=1 c_use_fpu=1 c_use_reorder_instr=1 c_unaligned_exceptions=0
c_ill_opcode_exception=0 c_div_zero_exception=0 c_fpu_exception=0 c_fsl_exception=0
c_use_stack_protection=0 c_use_interrupt=2 c_use_ext_brk=0 c_use_ext_nm_brk=0
c_use_mmu=0 c_mmu_dtlb_size=4 c_mmu_itlb_size=2 c_mmu_tlb_access=3
c_mmu_zones=16 c_mmu_privileged_instr=0 c_use_branch_target_cache=1 c_branch_target_cache_size=0
c_pc_width=32 c_pvr=0 c_pvr_user1=0x00 c_pvr_user2=0x00000000
c_dynamic_bus_sizing=0 c_reset_msr=0x00000000 c_opcode_0x0_illegal=0 c_debug_enabled=1
c_number_of_pc_brk=1 c_number_of_rd_addr_brk=0 c_number_of_wr_addr_brk=0 c_debug_event_counters=5
c_debug_latency_counters=1 c_debug_counter_width=32 c_debug_trace_size=8192 c_debug_profile_size=0
c_interrupt_is_edge=0 c_edge_is_positive=0 c_async_interrupt=1 c_fsl_links=0
c_use_extended_fsl_instr=0 c_m0_axis_data_width=32 c_s0_axis_data_width=32 c_m1_axis_data_width=32
c_s1_axis_data_width=32 c_m2_axis_data_width=32 c_s2_axis_data_width=32 c_m3_axis_data_width=32
c_s3_axis_data_width=32 c_m4_axis_data_width=32 c_s4_axis_data_width=32 c_m5_axis_data_width=32
c_s5_axis_data_width=32 c_m6_axis_data_width=32 c_s6_axis_data_width=32 c_m7_axis_data_width=32
c_s7_axis_data_width=32 c_m8_axis_data_width=32 c_s8_axis_data_width=32 c_m9_axis_data_width=32
c_s9_axis_data_width=32 c_m10_axis_data_width=32 c_s10_axis_data_width=32 c_m11_axis_data_width=32
c_s11_axis_data_width=32 c_m12_axis_data_width=32 c_s12_axis_data_width=32 c_m13_axis_data_width=32
c_s13_axis_data_width=32 c_m14_axis_data_width=32 c_s14_axis_data_width=32 c_m15_axis_data_width=32
c_s15_axis_data_width=32 c_icache_baseaddr=0x00000000 c_icache_highaddr=0x3FFFFFFF c_use_icache=0
c_allow_icache_wr=1 c_addr_tag_bits=17 c_cache_byte_size=8192 c_icache_line_len=4
c_icache_always_used=0 c_icache_streams=0 c_icache_victims=0 c_icache_force_tag_lutram=0
c_icache_data_width=0 c_m_axi_ic_thread_id_width=1 c_m_axi_ic_data_width=32 c_m_axi_ic_addr_width=32
c_m_axi_ic_user_value=31 c_m_axi_ic_awuser_width=5 c_m_axi_ic_aruser_width=5 c_m_axi_ic_wuser_width=1
c_m_axi_ic_ruser_width=1 c_m_axi_ic_buser_width=1 c_dcache_baseaddr=0x00000000 c_dcache_highaddr=0x3FFFFFFF
c_use_dcache=0 c_allow_dcache_wr=1 c_dcache_addr_tag=17 c_dcache_byte_size=8192
c_dcache_line_len=4 c_dcache_always_used=0 c_dcache_use_writeback=0 c_dcache_victims=0
c_dcache_force_tag_lutram=0 c_dcache_data_width=0 c_m_axi_dc_thread_id_width=1 c_m_axi_dc_data_width=32
c_m_axi_dc_addr_width=32 c_m_axi_dc_exclusive_access=0 c_m_axi_dc_user_value=31 c_m_axi_dc_awuser_width=5
c_m_axi_dc_aruser_width=5 c_m_axi_dc_wuser_width=1 c_m_axi_dc_ruser_width=1 c_m_axi_dc_buser_width=1
axi_crossbar_v2_1_axi_crossbar/1
iptotal=1 x_ipproduct=Vivado 2014.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_crossbar x_ipversion=2.1 x_ipcorerevision=2 x_iplanguage=VERILOG
c_family=artix7 c_num_slave_slots=1 c_num_master_slots=3 c_axi_id_width=1
c_axi_addr_width=32 c_axi_data_width=32 c_axi_protocol=2 c_num_addr_ranges=1
c_m_axi_base_addr=0x0000000041c0000000000000406000000000000041200000 c_m_axi_addr_width=0x000000100000001000000010 c_s_axi_base_id=0x00000000 c_s_axi_thread_id_width=0x00000000
c_axi_supports_user_signals=0 c_axi_awuser_width=1 c_axi_aruser_width=1 c_axi_wuser_width=1
c_axi_ruser_width=1 c_axi_buser_width=1 c_m_axi_write_connectivity=0x000000010000000100000001 c_m_axi_read_connectivity=0x000000010000000100000001
c_r_register=1 c_s_axi_single_thread=0x00000001 c_s_axi_write_acceptance=0x00000001 c_s_axi_read_acceptance=0x00000001
c_m_axi_write_issuing=0x000000010000000100000001 c_m_axi_read_issuing=0x000000010000000100000001 c_s_axi_arb_priority=0x00000000 c_m_axi_secure=0x000000000000000000000000
c_connectivity_mode=0
axi_intc/1
iptotal=1 x_ipproduct=Vivado 2014.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_intc x_ipversion=4.1 x_ipcorerevision=1 x_iplanguage=VERILOG
c_family=artix7 c_instance=axi_intc_inst c_s_axi_addr_width=9 c_s_axi_data_width=32
c_num_intr_inputs=2 c_num_sw_intr=0 c_kind_of_intr=0xfffffffd c_kind_of_edge=0xffffffff
c_kind_of_lvl=0xffffffff c_async_intr=0xFFFFFFFC c_num_sync_ff=2 c_ivar_reset_value=0x00000010
c_enable_async=0 c_has_ipr=1 c_has_sie=1 c_has_cie=1
c_has_ivr=1 c_has_ilr=0 c_irq_is_level=1 c_irq_active=0x1
c_disable_synchronizers=1 c_mb_clk_not_connected=1 c_has_fast=1 c_en_cascade_mode=0
c_cascade_master=0
axi_timer/1
iptotal=1 x_ipproduct=Vivado 2014.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_timer x_ipversion=2.0 x_ipcorerevision=4 x_iplanguage=VERILOG
c_family=artix7 c_count_width=32 c_one_timer_only=1 c_trig0_assert=1
c_trig1_assert=1 c_gen0_assert=1 c_gen1_assert=1 c_s_axi_data_width=32
c_s_axi_addr_width=5
axi_uartlite/1
iptotal=1 x_ipproduct=Vivado 2014.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_uartlite x_ipversion=2.0 x_ipcorerevision=4 x_iplanguage=VERILOG
c_family=artix7 c_s_axi_aclk_freq_hz=100000000 c_s_axi_addr_width=4 c_s_axi_data_width=32
c_baudrate=9600 c_data_bits=8 c_use_parity=0 c_odd_parity=0
blk_mem_gen_v8_2/1
iptotal=1 x_ipproduct=Vivado 2014.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=blk_mem_gen x_ipversion=8.2 x_ipcorerevision=0 x_iplanguage=VERILOG
c_family=artix7 c_xdevicefamily=artix7 c_elaboration_dir=./ c_interface_type=0
c_axi_type=1 c_axi_slave_type=0 c_use_bram_block=1 c_enable_32bit_address=1
c_ctrl_ecc_algo=NONE c_has_axi_id=0 c_axi_id_width=4 c_mem_type=2
c_byte_size=8 c_algorithm=1 c_prim_type=1 c_load_init_file=0
c_init_file_name=no_coe_file_loaded c_init_file=design_1_lmb_bram_0.mem c_use_default_data=0 c_default_data=0
c_has_rsta=1 c_rst_priority_a=CE c_rstram_a=0 c_inita_val=0
c_has_ena=1 c_has_regcea=0 c_use_byte_wea=1 c_wea_width=4
c_write_mode_a=WRITE_FIRST c_write_width_a=32 c_read_width_a=32 c_write_depth_a=32768
c_read_depth_a=32768 c_addra_width=32 c_has_rstb=1 c_rst_priority_b=CE
c_rstram_b=0 c_initb_val=0 c_has_enb=1 c_has_regceb=0
c_use_byte_web=1 c_web_width=4 c_write_mode_b=WRITE_FIRST c_write_width_b=32
c_read_width_b=32 c_write_depth_b=32768 c_read_depth_b=32768 c_addrb_width=32
c_has_mem_output_regs_a=0 c_has_mem_output_regs_b=0 c_has_mux_output_regs_a=0 c_has_mux_output_regs_b=0
c_mux_pipeline_stages=0 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0 c_use_softecc=0
c_use_ecc=0 c_en_ecc_pipe=0 c_has_injecterr=0 c_sim_collision_check=ALL
c_common_clk=0 c_disable_warn_bhv_coll=0 c_en_sleep_pin=0 c_disable_warn_bhv_range=0
c_count_36k_bram=32 c_count_18k_bram=0 c_est_power_summary=Estimated Power for IP _ 20.388 mW
clk_wiz_v5_1/1
iptotal=1 component_name=design_1_clk_wiz_1_0 use_phase_alignment=true use_min_o_jitter=false
use_max_i_jitter=false use_dyn_phase_shift=false use_inclk_switchover=false use_dyn_reconfig=false
enable_axi=0 feedback_source=FDBK_AUTO primitive=MMCM num_out_clk=1
clkin1_period=10.0 clkin2_period=10.0 use_power_down=false use_reset=true
use_locked=true use_inclk_stopped=false feedback_type=SINGLE clock_mgr_type=NA
manual_override=false
lmb_bram_if_cntlr/1
iptotal=1 x_ipproduct=Vivado 2014.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=lmb_bram_if_cntlr x_ipversion=4.0 x_ipcorerevision=3 x_iplanguage=VERILOG
c_family=artix7 c_highaddr=0x0001FFFF c_baseaddr=0x00000000 c_mask=0x40000000
c_mask1=0x00800000 c_mask2=0x00800000 c_mask3=0x00800000 c_lmb_awidth=32
c_lmb_dwidth=32 c_ecc=0 c_interconnect=0 c_fault_inject=0
c_ce_failing_registers=0 c_ue_failing_registers=0 c_ecc_status_registers=0 c_ecc_onoff_register=0
c_ecc_onoff_reset_value=1 c_ce_counter_width=0 c_write_access=2 c_num_lmb=1
c_s_axi_ctrl_addr_width=32 c_s_axi_ctrl_data_width=32
lmb_bram_if_cntlr/2
iptotal=1 x_ipproduct=Vivado 2014.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=lmb_bram_if_cntlr x_ipversion=4.0 x_ipcorerevision=3 x_iplanguage=VERILOG
c_family=artix7 c_highaddr=0x0001FFFF c_baseaddr=0x00000000 c_mask=0x00000000
c_mask1=0x00800000 c_mask2=0x00800000 c_mask3=0x00800000 c_lmb_awidth=32
c_lmb_dwidth=32 c_ecc=0 c_interconnect=0 c_fault_inject=0
c_ce_failing_registers=0 c_ue_failing_registers=0 c_ecc_status_registers=0 c_ecc_onoff_register=0
c_ecc_onoff_reset_value=1 c_ce_counter_width=0 c_write_access=2 c_num_lmb=1
c_s_axi_ctrl_addr_width=32 c_s_axi_ctrl_data_width=32
lmb_v10/1
iptotal=1 x_ipproduct=Vivado 2014.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=lmb_v10 x_ipversion=3.0 x_ipcorerevision=3 x_iplanguage=VERILOG
c_lmb_num_slaves=1 c_lmb_dwidth=32 c_lmb_awidth=32 c_ext_reset_high=1
lmb_v10/2
iptotal=1 x_ipproduct=Vivado 2014.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=lmb_v10 x_ipversion=3.0 x_ipcorerevision=3 x_iplanguage=VERILOG
c_lmb_num_slaves=1 c_lmb_dwidth=32 c_lmb_awidth=32 c_ext_reset_high=1
proc_sys_reset/1
iptotal=1 x_ipproduct=Vivado 2014.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=proc_sys_reset x_ipversion=5.0 x_ipcorerevision=4 x_iplanguage=VERILOG
c_family=artix7 c_ext_rst_width=4 c_aux_rst_width=4 c_ext_reset_high=0
c_aux_reset_high=0 c_num_bus_rst=1 c_num_perp_rst=1 c_num_interconnect_aresetn=1
c_num_perp_aresetn=1
xlconcat/1
iptotal=1 x_ipproduct=Vivado 2014.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=xlconcat x_ipversion=2.0 x_ipcorerevision=-1 x_iplanguage=VERILOG
num_ports=2 in0_width=1 in1_width=1 in2_width=1
in3_width=1 in4_width=1 in5_width=1 in6_width=1
in7_width=1 in8_width=1 in9_width=1 in10_width=1
in11_width=1 in12_width=1 in13_width=1 in14_width=1
in15_width=1 dout_width=2

report_utilization
slice_logic
slice_luts_used=2956 slice_luts_loced=0 slice_luts_available=63400 slice_luts_util_percentage=4.66
lut_as_logic_used=2781 lut_as_logic_loced=0 lut_as_logic_available=63400 lut_as_logic_util_percentage=4.38
lut_as_memory_used=175 lut_as_memory_loced=0 lut_as_memory_available=19000 lut_as_memory_util_percentage=0.92
lut_as_distributed_ram_used=96 lut_as_distributed_ram_loced=0 lut_as_shift_register_used=79 lut_as_shift_register_loced=0
slice_registers_used=2435 slice_registers_loced=0 slice_registers_available=126800 slice_registers_util_percentage=1.92
register_as_flip_flop_used=2435 register_as_flip_flop_loced=0 register_as_flip_flop_available=126800 register_as_flip_flop_util_percentage=1.92
register_as_latch_used=0 register_as_latch_loced=0 register_as_latch_available=126800 register_as_latch_util_percentage=0.00
f7_muxes_used=46 f7_muxes_loced=0 f7_muxes_available=31700 f7_muxes_util_percentage=0.14
f8_muxes_used=1 f8_muxes_loced=0 f8_muxes_available=15850 f8_muxes_util_percentage=<0.01
slice_used=1029 slice_loced=0 slice_available=15850 slice_util_percentage=6.49
slicel_used=674 slicel_loced=0 slicem_used=355 slicem_loced=0
lut_as_logic_used=2781 lut_as_logic_loced=0 lut_as_logic_available=63400 lut_as_logic_util_percentage=4.38
using_o5_output_only_used=2 using_o5_output_only_loced= using_o6_output_only_used=2257 using_o6_output_only_loced=
using_o5_and_o6_used=522 using_o5_and_o6_loced= lut_as_memory_used=175 lut_as_memory_loced=0
lut_as_memory_available=19000 lut_as_memory_util_percentage=0.92 lut_as_distributed_ram_used=96 lut_as_distributed_ram_loced=0
using_o5_output_only_used=0 using_o5_output_only_loced= using_o6_output_only_used=0 using_o6_output_only_loced=
using_o5_and_o6_used=96 using_o5_and_o6_loced= lut_as_shift_register_used=79 lut_as_shift_register_loced=0
using_o5_output_only_used=3 using_o5_output_only_loced= using_o6_output_only_used=28 using_o6_output_only_loced=
using_o5_and_o6_used=48 using_o5_and_o6_loced= lut_flip_flop_pairs_used=3371 lut_flip_flop_pairs_loced=0
lut_flip_flop_pairs_available=63400 lut_flip_flop_pairs_util_percentage=5.31 fully_used_lut_ff_pairs_used=1652 fully_used_lut_ff_pairs_loced=
lut_ff_pairs_with_unused_lut_used=420 lut_ff_pairs_with_unused_lut_loced= lut_ff_pairs_with_unused_flip_flop_used=1299 lut_ff_pairs_with_unused_flip_flop_loced=
unique_control_sets_used=107 minimum_number_of_registers_lost_to_control_set_restriction_used=357(Lost)
memory
block_ram_tile_used=33 block_ram_tile_loced=0 block_ram_tile_available=135 block_ram_tile_util_percentage=24.44
ramb36_fifo*_used=33 ramb36_fifo*_loced=0 ramb36_fifo*_available=135 ramb36_fifo*_util_percentage=24.44
ramb36e1_only_used=33 ramb18_used=0 ramb18_loced=0 ramb18_available=270
ramb18_util_percentage=0.00
dsp
dsps_used=5 dsps_loced=0 dsps_available=240 dsps_util_percentage=2.08
dsp48e1_only_used=5
clocking
bufgctrl_used=4 bufgctrl_loced=0 bufgctrl_available=32 bufgctrl_util_percentage=12.50
bufio_used=0 bufio_loced=0 bufio_available=24 bufio_util_percentage=0.00
mmcme2_adv_used=1 mmcme2_adv_loced=0 mmcme2_adv_available=6 mmcme2_adv_util_percentage=16.66
plle2_adv_used=0 plle2_adv_loced=0 plle2_adv_available=6 plle2_adv_util_percentage=0.00
bufmrce_used=0 bufmrce_loced=0 bufmrce_available=12 bufmrce_util_percentage=0.00
bufhce_used=0 bufhce_loced=0 bufhce_available=96 bufhce_util_percentage=0.00
bufr_used=0 bufr_loced=0 bufr_available=24 bufr_util_percentage=0.00
specific_feature
bscane2_used=1 bscane2_loced=1 bscane2_available=4 bscane2_util_percentage=25.00
capturee2_used=0 capturee2_loced=0 capturee2_available=1 capturee2_util_percentage=0.00
dna_port_used=0 dna_port_loced=0 dna_port_available=1 dna_port_util_percentage=0.00
efuse_usr_used=0 efuse_usr_loced=0 efuse_usr_available=1 efuse_usr_util_percentage=0.00
frame_ecce2_used=0 frame_ecce2_loced=0 frame_ecce2_available=1 frame_ecce2_util_percentage=0.00
icape2_used=0 icape2_loced=0 icape2_available=2 icape2_util_percentage=0.00
pcie_2_1_used=0 pcie_2_1_loced=0 pcie_2_1_available=1 pcie_2_1_util_percentage=0.00
startupe2_used=0 startupe2_loced=0 startupe2_available=1 startupe2_util_percentage=0.00
xadc_used=0 xadc_loced=0 xadc_available=1 xadc_util_percentage=0.00
primitives
fdre_used=2165 fdre_functional_category=Flop & Latch lut6_used=1069 lut6_functional_category=LUT
lut3_used=848 lut3_functional_category=LUT lut5_used=560 lut5_functional_category=LUT
lut4_used=442 lut4_functional_category=LUT lut2_used=355 lut2_functional_category=LUT
fdce_used=206 fdce_functional_category=Flop & Latch ramd32_used=160 ramd32_functional_category=Distributed Memory
carry4_used=155 carry4_functional_category=CarryLogic srl16e_used=119 srl16e_functional_category=Distributed Memory
fdse_used=59 fdse_functional_category=Flop & Latch muxf7_used=46 muxf7_functional_category=MuxFx
ramb36e1_used=33 ramb36e1_functional_category=Block Memory rams32_used=32 rams32_functional_category=Distributed Memory
lut1_used=29 lut1_functional_category=LUT srlc16e_used=7 srlc16e_functional_category=Distributed Memory
fdpe_used=5 fdpe_functional_category=Flop & Latch dsp48e1_used=5 dsp48e1_functional_category=Block Arithmetic
ibuf_used=4 ibuf_functional_category=IO bufg_used=4 bufg_functional_category=Clock
srlc32e_used=1 srlc32e_functional_category=Distributed Memory obuf_used=1 obuf_functional_category=IO
muxf8_used=1 muxf8_functional_category=MuxFx mmcme2_adv_used=1 mmcme2_adv_functional_category=Clock
bscane2_used=1 bscane2_functional_category=Others and2b1l_used=1 and2b1l_functional_category=Others
io_standard
pci33_3=0 lvcmos12=0 sstl135=0 lvttl=0
diff_sstl18_ii=0 hstl_i=0 mobile_ddr=0 hsul_12=0
lvcmos25=0 sstl135_r=0 lvcmos33=1 diff_sstl15=0
hstl_ii=0 lvcmos18=0 lvcmos15=0 hstl_i_18=0
diff_hsul_12=0 hstl_ii_18=0 sstl18_i=0 sstl18_ii=0
sstl15=0 sstl15_r=0 lvds_25=0 diff_hstl_i=0
rsds_25=0 diff_hstl_ii=0 tmds_33=0 diff_hstl_i_18=0
mini_lvds_25=0 diff_hstl_ii_18=0 ppds_25=0 diff_sstl18_i=0
diff_sstl15_r=0 diff_sstl135=0 diff_sstl135_r=0 diff_mobile_ddr=0
blvds_25=0

router
usage
lut=3170 ff=2435 bram36=33 bram18=0
ctrls=107 dsp=5 iob=5 bufg=0
global_clocks=4 pll=0 bufr=0 nets=7677
movable_instances=6465 pins=45975 bogomips=0 high_fanout_nets=5
effort=2 threads=2 router_timing_driven=1 timing_constraints_exist=1
congestion_level=1 estimated_expansions=7583292 actual_expansions=12391652 router_runtime=259.663000