Most of the course evaluation is based on a project that you will do using the Xilinx tools and the XUP board. Learning to use the tools quickly is important so that you can have enough time to do the project. The key is to learn enough of the tools to do what you need to do.
The TAs will be monitoring the discussion board for activity and respond when they can.
Please do not email the TAs directly unless it is for something specific to you.
As mentioned under Grading, there are Community bonus marks for participating on the discussion board.
Instructions to get a board and the form to get the install key are on this form which must be returned by the date specified in the timeline below.
There will be three lab periods where you can get help with the lab modules during the lab period. The first lab will be an introductory lab to help you get started. There will not be any grading done during these lab periods. The TAs are there to help so use that time effectively.
You will need to work on these modules outside of the lab periods. The tools can take a long time to do a compile so you won't be able to finish everything during lab hours and you'll spend a lot of time waiting anyways. Plan on having something else to do in parallel.
During the lab test period you will be assigned a specific time slot where you will be graded on the lab test design and a ModelSim simulation. You must become comfortable with ModelSim very quickly as you should be doing lots of simulation so this is your incentive to learn.
The requirements are given here. This will be the 10% of your final grade assigned to the lab test.
The basic guideline is that your project should incorporate at least one MicroBlaze processor running a part of your application and a hardware block of your own design. The remainder of the project can use and software or hardware IP that you find useful.
You will need a block diagram of your system. The example shown here is good. The diagram should show all datapath connections. Note that any software IP should be indicated within the processor blocks running that software.
The relevant documents are linked in the Activity descriptions.
|Week No.||Completion by end of||Grades||Activity|
|1||Jan 5-7||First week of classes, no labs|
|2||Jan 12 lab||Submit Board and Tool Request form|
|2||Jan 12 lab||Sign out boards before lab|
|3||Jan 17 lecture||Draft proposal due at start of lecture|
|3||Jan 19 lab||Project proposal feedback|
|4||Jan 26 lab||10%||Submit formal project proposal. It will need a good block diagram. The first milestone in the proposal will be checked on Feb. 9. The milestone can be modified up until the Feb. 2 lab.|
|5||Feb 2 lab||10%||Grading of your lab test|
|6||Feb 9 lab||Show Milestone 1 - Start milestone demos and weekly progress reports (25% total)|
|R||Feb 21-25||Reading week|
|12||Mar 29-31||ECE Design Fair|
|13||Apr 4 lecture||17.5%||Individual report due at start of lecture|
|13||Apr 4 lecture||17.5%||Group report due at start of lecture|
|13||Apr 6 lab||20%||Project final demos|