# -------------------------------------------------------------
#   Copyright(C) 2003 by Xilinx, Inc. All rights reserved.   --
#                                                            --
#   This copyright notice must be retained as part           --
#   of this text at all times.                               --
# -------------------------------------------------------------

ATTRIBUTE VENDOR = Xilinx
ATTRIBUTE SPEC_URL = www.xilinx.com
ATTRIBUTE CONTACT_INFO_URL=http://www.xilinx.com/support/techsup/tappinfo.htm

ATTRIBUTE NAME = Virtex-II Multimedia FF896 Development Board

ATTRIBUTE REVISION = 1

ATTRIBUTE DESC = Xilinx Virtex-II Multimedia FF896 Development Board Revision ?

ATTRIBUTE LONG_DESC = 'The Xilinx Virtex-II Multimedia FF896 development board provides a complete development platform for designing and verifying applications using a Xilinx Virtex-II).  This boards includes 10MB of ZBT Memory, two clock sources, 1 RS232 serial port, 4 DIP switches, and 2 LEDs. USER_INPUT0 is used as active high reset.'

BEGIN IO_INTERFACE
  ATTRIBUTE IOTYPE = XIL_CLOCK_V1
   ATTRIBUTE INSTANCE =clk_27
   PARAMETER CLK_FREQ =27000000, IO_IS=clk_freq, RANGE=(27000000) # 27 Mhz
   PORT CLK.CAN.HS = CONN_CLK.27 , IO_IS=ext_clk
END

BEGIN IO_INTERFACE
  ATTRIBUTE IOTYPE = XIL_CLOCK_V1
   ATTRIBUTE INSTANCE =clk_50
   PARAMETER CLK_FREQ =50000000, IO_IS=clk_freq, RANGE=(50000000) # 50 Mhz
   PORT CLK.CAN.HS = CONN_CLK.50 , IO_IS=ext_clk
END

BEGIN IO_INTERFACE
  ATTRIBUTE IOTYPE = XIL_RESET_V1
   ATTRIBUTE INSTANCE =rst_0
   PARAMETER RST_POLARITY =1, IO_IS=polarity, VALUE_NOTE=Active High
   PORT FPGA.RESET =  CONN_FPGA.RESET, IO_IS=ext_rst
END

BEGIN IO_INTERFACE
  ATTRIBUTE IOTYPE = XIL_GPIO_V1
   ATTRIBUTE INSTANCE = LEDs_2Bit
   PARAMETER num_bits =2, IO_IS=num_bits
   PARAMETER is_dual=0, IO_IS=is_dual
   PARAMETER all_inputs =0, IO_IS=all_inputs   # All outputs
   PARAMETER bidir_data=0, IO_IS=is_bidir     # Non-bidir data pins

   PORT LED1 = CONN_LED1, IO_IS = gpio_data_out[0], INITIALVAL = VCC
   PORT LED2 = CONN_LED2, IO_IS = gpio_data_out[1], INITIALVAL = VCC
END

BEGIN IO_INTERFACE
  ATTRIBUTE IOTYPE = XIL_UART_V1
   ATTRIBUTE INSTANCE=RS232
   PORT RXD = CONN_RXD, IO_IS=serial_in
   PORT TXD = CONN_TXD, IO_IS=serial_out, INITIALVAL = GND
   PORT CTS = CONN_CTS, IO_IS=clear_to_send
   PORT RTS = CONN_RTS, IO_IS=req_to_send, INITIALVAL = GND
END       

# LTX972 Ethernet MAC: 
BEGIN IO_INTERFACE
  ATTRIBUTE IOTYPE = XIL_ETHERNET_V1
  ATTRIBUTE INSTANCE = Ethernet_MAC
  ATTRIBUTE ALERT = A special signal called STARTUP should be driven high after the system is stable in order for Ethernet to work properly.  See the board user guide for detail. 
  PORT TXSLEW0  = phy_slew0, IO_IS=slew1,      INITIALVAL = VCC  # (LTX972 PIN 5)
  PORT TXSLEW1  = phy_slew1, IO_IS=slew2,      INITIALVAL = VCC  # (LTX972 PIN 6)
  PORT RESET    = phy_rst_n, IO_IS=PHY_RESETn, INITIALVAL = VCC  # (LTX972 PIN 4)
  PORT MDINT    = phy_mii_int_n, IO_IS=mii_int_n   # (LTX972 PIN 64)
  PORT CRS      = phy_crs,       IO_IS=ETH_CRS     # (LTX972 PIN 63)
  PORT COL      = phy_col,       IO_IS=ETH_COL     # (LTX972 PIN 62)
  PORT TXD3     = phy_tx_data_3, IO_IS = ETH_TXD[3]  # (LTX972 PIN 60)
  PORT TXD2     = phy_tx_data_2, IO_IS = ETH_TXD[2]  # (LTX972 PIN 59)
  PORT TXD1     = phy_tx_data_1, IO_IS = ETH_TXD[1]  # (LTX972 PIN 58)
  PORT TXD0     = phy_tx_data_0, IO_IS = ETH_TXD[0]  # (LTX972 PIN 57)
  PORT TX_EN    = phy_tx_en,     IO_IS=ETH_TXEN    # (LTX972 PIN 56)
  PORT TX_CLK   = phy_tx_clk,    IO_IS=ETH_TXC     # (LTX972 PIN 55)
  PORT TX_ER    = phy_tx_er,     IO_IS=ETH_TXER    # (LTX972 PIN 54)
  PORT RX_ER    = phy_rx_er,     IO_IS=ETH_RXER    # (LTX972 PIN 53)
  PORT RX_CLK   = phy_rx_clk,    IO_IS=ETH_RXC     # (LTX972 PIN 52)
  PORT RX_DV    = phy_dv,        IO_IS=ETH_RXDV    # (LTX972 PIN 49)
  PORT RXD0     = phy_rx_data_0, IO_IS = ETH_RXD[0]  # (LTX972 PIN 48)
  PORT RXD1     = phy_rx_data_1, IO_IS = ETH_RXD[1]  # (LTX972 PIN 47)
  PORT RXD2     = phy_rx_data_2, IO_IS = ETH_RXD[2]  # (LTX972 PIN 46)
  PORT RXD3     = phy_rx_data_3, IO_IS = ETH_RXD[3]  # (LTX972 PIN 45)
  PORT PHY_MDC  = phy_mii_clk,   IO_IS=ETH_MDC     # (LTX972 PIN 43)
  PORT PHY_MDIO = phy_mii_data,  IO_IS=ETH_MDIO    # (LTX972 PIN 42)
END


BEGIN IO_INTERFACE
  ATTRIBUTE IOTYPE = XIL_EMC_V1
   ATTRIBUTE INSTANCE = ZBT_512Kx32
   PARAMETER C_NUM_BANKS_MEM = 1, IO_IS=C_NUM_BANKS_MEM
   PARAMETER C_DEV_MIR_ENABLE = 0, IO_IS=C_DEV_MIR_ENABLE

####### Bank0 ########
   PARAMETER C_MEM0_BASEADDR = 0x0, IO_IS=C_MEM0_BASEADDR, SHORT_DESC=ZBT_512Kx32_Bank0, MEMORY_TYPE=ZBT
   PARAMETER C_MEM0_HIGHADDR = 0x1FFFFF, IO_IS=C_MEM0_HIGHADDR
   PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 0, IO_IS=C_INCLUDE_DATAWIDTH_MATCHING_0
   PARAMETER C_SYNCH_MEM_0 = 1, IO_IS=C_SYNCH_MEM_0
   PARAMETER C_MEM0_WIDTH = 32, IO_IS=C_MEM_WIDTH
   
   PORT BANK0_ADDR0 = CONN_BANK0_ADDR0, IO_IS = emc_addr[29]
   PORT BANK0_ADDR1 = CONN_BANK0_ADDR1, IO_IS = emc_addr[28]
   PORT BANK0_ADDR2 = CONN_BANK0_ADDR2, IO_IS = emc_addr[27]
   PORT BANK0_ADDR3 = CONN_BANK0_ADDR3, IO_IS = emc_addr[26]
   PORT BANK0_ADDR4 = CONN_BANK0_ADDR4, IO_IS = emc_addr[25]
   PORT BANK0_ADDR5 = CONN_BANK0_ADDR5, IO_IS = emc_addr[24]
   PORT BANK0_ADDR6 = CONN_BANK0_ADDR6, IO_IS = emc_addr[23]
   PORT BANK0_ADDR7 = CONN_BANK0_ADDR7, IO_IS = emc_addr[22]
   PORT BANK0_ADDR8 = CONN_BANK0_ADDR8, IO_IS = emc_addr[21]
   PORT BANK0_ADDR9 = CONN_BANK0_ADDR9, IO_IS = emc_addr[20]
   PORT BANK0_ADDR10 = CONN_BANK0_ADDR10, IO_IS = emc_addr[19]
   PORT BANK0_ADDR11 = CONN_BANK0_ADDR11, IO_IS = emc_addr[18]
   PORT BANK0_ADDR12 = CONN_BANK0_ADDR12, IO_IS = emc_addr[17]
   PORT BANK0_ADDR13 = CONN_BANK0_ADDR13, IO_IS = emc_addr[16]
   PORT BANK0_ADDR14 = CONN_BANK0_ADDR14, IO_IS = emc_addr[15]
   PORT BANK0_ADDR15 = CONN_BANK0_ADDR15, IO_IS = emc_addr[14]
   PORT BANK0_ADDR16 = CONN_BANK0_ADDR16, IO_IS = emc_addr[13]
   PORT BANK0_ADDR17 = CONN_BANK0_ADDR17, IO_IS = emc_addr[12]
   PORT BANK0_ADDR18 = CONN_BANK0_ADDR18, IO_IS = emc_addr[11]

   PORT BANK0_DATA_A0 = CONN_BANK0_DATA_A0, IO_IS = emc_data[31]
   PORT BANK0_DATA_A1 = CONN_BANK0_DATA_A1, IO_IS = emc_data[30]
   PORT BANK0_DATA_A2 = CONN_BANK0_DATA_A2, IO_IS = emc_data[29]
   PORT BANK0_DATA_A3 = CONN_BANK0_DATA_A3, IO_IS = emc_data[28]
   PORT BANK0_DATA_A4 = CONN_BANK0_DATA_A4, IO_IS = emc_data[27]
   PORT BANK0_DATA_A5 = CONN_BANK0_DATA_A5, IO_IS = emc_data[26]
   PORT BANK0_DATA_A6 = CONN_BANK0_DATA_A6, IO_IS = emc_data[25]
   PORT BANK0_DATA_A7 = CONN_BANK0_DATA_A7, IO_IS = emc_data[24]

   PORT BANK0_DATA_B0 = CONN_BANK0_DATA_B0, IO_IS = emc_data[23]
   PORT BANK0_DATA_B1 = CONN_BANK0_DATA_B1, IO_IS = emc_data[22]
   PORT BANK0_DATA_B2 = CONN_BANK0_DATA_B2, IO_IS = emc_data[21]
   PORT BANK0_DATA_B3 = CONN_BANK0_DATA_B3, IO_IS = emc_data[20]
   PORT BANK0_DATA_B4 = CONN_BANK0_DATA_B4, IO_IS = emc_data[19]
   PORT BANK0_DATA_B5 = CONN_BANK0_DATA_B5, IO_IS = emc_data[18]
   PORT BANK0_DATA_B6 = CONN_BANK0_DATA_B6, IO_IS = emc_data[17]
   PORT BANK0_DATA_B7 = CONN_BANK0_DATA_B7, IO_IS = emc_data[16]

   PORT BANK0_DATA_C0 = CONN_BANK0_DATA_C0, IO_IS = emc_data[15]
   PORT BANK0_DATA_C1 = CONN_BANK0_DATA_C1, IO_IS = emc_data[14]
   PORT BANK0_DATA_C2 = CONN_BANK0_DATA_C2, IO_IS = emc_data[13]
   PORT BANK0_DATA_C3 = CONN_BANK0_DATA_C3, IO_IS = emc_data[12]
   PORT BANK0_DATA_C4 = CONN_BANK0_DATA_C4, IO_IS = emc_data[11]
   PORT BANK0_DATA_C5 = CONN_BANK0_DATA_C5, IO_IS = emc_data[10]
   PORT BANK0_DATA_C6 = CONN_BANK0_DATA_C6, IO_IS = emc_data[9]
   PORT BANK0_DATA_C7 = CONN_BANK0_DATA_C7, IO_IS = emc_data[8]

   PORT BANK0_DATA_D0 = CONN_BANK0_DATA_D0, IO_IS = emc_data[7]
   PORT BANK0_DATA_D1 = CONN_BANK0_DATA_D1, IO_IS = emc_data[6]
   PORT BANK0_DATA_D2 = CONN_BANK0_DATA_D2, IO_IS = emc_data[5]
   PORT BANK0_DATA_D3 = CONN_BANK0_DATA_D3, IO_IS = emc_data[4]
   PORT BANK0_DATA_D4 = CONN_BANK0_DATA_D4, IO_IS = emc_data[3]
   PORT BANK0_DATA_D5 = CONN_BANK0_DATA_D5, IO_IS = emc_data[2]
   PORT BANK0_DATA_D6 = CONN_BANK0_DATA_D6, IO_IS = emc_data[1]
   PORT BANK0_DATA_D7 = CONN_BANK0_DATA_D7, IO_IS = emc_data[0]

   PORT BANK0_WEND_Z = CONN_BANK0_WEND_Z, IO_IS = emc_ben[0]
   PORT BANK0_WENC_Z = CONN_BANK0_WENC_Z, IO_IS = emc_ben[1]
   PORT BANK0_WENB_Z = CONN_BANK0_WENB_Z, IO_IS = emc_ben[2]
   PORT BANK0_WENA_Z = CONN_BANK0_WENA_Z, IO_IS = emc_ben[3]
   PORT BANK0_WEN_Z = CONN_BANK0_WEN_Z, IO_IS=emc_wen	
   PORT BANK0_OEN_Z = CONN_BANK0_OEN_Z, IO_IS = emc_oen[0]
   PORT BANK0_CEN_Z = CONN_BANK0_CEN_Z, IO_IS = emc_csn[0]
   PORT BANK0_CLKEN_Z = CONN_BANK0_CLKEN_Z, IO_IS=emc_cken
   PORT BANK0_ADV_LDZ = CONN_BANK0_ADV_LDZ, IO_IS=emc_adv_ldn
   PORT ZBT_CLK_OUT = CONN_ZBT_CLK, IO_IS=EMC_CLK_OUT
END


BEGIN FPGA
  ATTRIBUTE INSTANCE = fpga_0
  ATTRIBUTE FAMILY = virtex2
  ATTRIBUTE  DEVICE =  XC2V2000
  ATTRIBUTE PACKAGE =  FF896
  ATTRIBUTE SPEED_GRADE =  -4
  ATTRIBUTE JTAG_POSITION = 2
          
  ### CLOCK ###
  PORT CLK_0 = CONN_CLK.27 , UCF_NET_STRING=("LOC=AH15")
  PORT CLK_0 = CONN_CLK.50 , UCF_NET_STRING=("LOC=AD16")
          
  ### RESET ###
  PORT RESET = CONN_FPGA.RESET, UCF_NET_STRING=("LOC=D10")

  ### GPIO ###
  PORT LED1 = CONN_LED1, UCF_NET_STRING=("LOC=B27")
  PORT LED2 = CONN_LED2, UCF_NET_STRING=("LOC=B22")
       
  ### UART ###
  PORT RXD = CONN_RXD, UCF_NET_STRING=("LOC=C8")
  PORT TXD = CONN_TXD, UCF_NET_STRING=("LOC=C9")
  PORT CTS = CONN_CTS, UCF_NET_STRING=("LOC=F11")
  PORT RTS = CONN_RTS, UCF_NET_STRING=("LOC=B8")

  ### ZBT Memory ###
   PORT ZBT_CLOCK = CONN_ZBT_CLK,   UCF_NET_STRING=("LOC=G27", "FAST")
  ### ZBT Bank0 ###
   PORT BANK0_ADDR0 = CONN_BANK0_ADDR0,  UCF_NET_STRING=("LOC=T23", "FAST")
   PORT BANK0_ADDR1 = CONN_BANK0_ADDR1,  UCF_NET_STRING=("LOC=U23", "FAST")
   PORT BANK0_ADDR2 = CONN_BANK0_ADDR2,  UCF_NET_STRING=("LOC=AB29", "FAST")
   PORT BANK0_ADDR3 = CONN_BANK0_ADDR3,  UCF_NET_STRING=("LOC=AA29", "FAST")
   PORT BANK0_ADDR4 = CONN_BANK0_ADDR4,  UCF_NET_STRING=("LOC=AA27", "FAST")
   PORT BANK0_ADDR5 = CONN_BANK0_ADDR5,  UCF_NET_STRING=("LOC=AB27", "FAST")
   PORT BANK0_ADDR6 = CONN_BANK0_ADDR6,  UCF_NET_STRING=("LOC=H25", "FAST")
   PORT BANK0_ADDR7 = CONN_BANK0_ADDR7,  UCF_NET_STRING=("LOC=G25", "FAST")
   PORT BANK0_ADDR8 = CONN_BANK0_ADDR8,  UCF_NET_STRING=("LOC=G28", "FAST")
   PORT BANK0_ADDR9 = CONN_BANK0_ADDR9,  UCF_NET_STRING=("LOC=H29", "FAST")
   PORT BANK0_ADDR10 = CONN_BANK0_ADDR10,  UCF_NET_STRING=("LOC=U27", "FAST")
   PORT BANK0_ADDR11 = CONN_BANK0_ADDR11,  UCF_NET_STRING=("LOC=T27", "FAST")
   PORT BANK0_ADDR12 = CONN_BANK0_ADDR12,  UCF_NET_STRING=("LOC=V29", "FAST")
   PORT BANK0_ADDR13 = CONN_BANK0_ADDR13,  UCF_NET_STRING=("LOC=U29", "FAST")
   PORT BANK0_ADDR14 = CONN_BANK0_ADDR14,  UCF_NET_STRING=("LOC=T24", "FAST")
   PORT BANK0_ADDR15 = CONN_BANK0_ADDR15,  UCF_NET_STRING=("LOC=T25", "FAST")
   PORT BANK0_ADDR16 = CONN_BANK0_ADDR16,  UCF_NET_STRING=("LOC=U28", "FAST")
   PORT BANK0_ADDR17 = CONN_BANK0_ADDR17,  UCF_NET_STRING=("LOC=F28", "FAST")
   PORT BANK0_ADDR18 = CONN_BANK0_ADDR18,   UCF_NET_STRING=("LOC=L23", "FAST")

   PORT BANK0_DATA_A0 = CONN_BANK0_DATA_A0,   UCF_NET_STRING=("LOC=T30", "FAST")
   PORT BANK0_DATA_A1 = CONN_BANK0_DATA_A1,   UCF_NET_STRING=("LOC=P28", "FAST")
   PORT BANK0_DATA_A2 = CONN_BANK0_DATA_A2,   UCF_NET_STRING=("LOC=R25", "FAST")
   PORT BANK0_DATA_A3 = CONN_BANK0_DATA_A3,   UCF_NET_STRING=("LOC=R29", "FAST")
   PORT BANK0_DATA_A4 = CONN_BANK0_DATA_A4,   UCF_NET_STRING=("LOC=R27", "FAST")
   PORT BANK0_DATA_A5 = CONN_BANK0_DATA_A5,   UCF_NET_STRING=("LOC=R23", "FAST")
   PORT BANK0_DATA_A6 = CONN_BANK0_DATA_A6,   UCF_NET_STRING=("LOC=N30", "FAST")
   PORT BANK0_DATA_A7 = CONN_BANK0_DATA_A7,   UCF_NET_STRING=("LOC=K26", "FAST")

   PORT BANK0_DATA_B0 = CONN_BANK0_DATA_B0,   UCF_NET_STRING=("LOC=M25", "FAST")
   PORT BANK0_DATA_B1 = CONN_BANK0_DATA_B1,   UCF_NET_STRING=("LOC=J29", "FAST")
   PORT BANK0_DATA_B2 = CONN_BANK0_DATA_B2,   UCF_NET_STRING=("LOC=K27", "FAST")
   PORT BANK0_DATA_B3 = CONN_BANK0_DATA_B3,   UCF_NET_STRING=("LOC=L24", "FAST")
   PORT BANK0_DATA_B4 = CONN_BANK0_DATA_B4,   UCF_NET_STRING=("LOC=H27", "FAST")
   PORT BANK0_DATA_B5 = CONN_BANK0_DATA_B5,   UCF_NET_STRING=("LOC=H26", "FAST")
   PORT BANK0_DATA_B6 = CONN_BANK0_DATA_B6,   UCF_NET_STRING=("LOC=K25", "FAST")
   PORT BANK0_DATA_B7 = CONN_BANK0_DATA_B7,   UCF_NET_STRING=("LOC=H28", "FAST")

   PORT BANK0_DATA_C0 = CONN_BANK0_DATA_C0,   UCF_NET_STRING=("LOC=J25", "FAST")
   PORT BANK0_DATA_C1 = CONN_BANK0_DATA_C1,   UCF_NET_STRING=("LOC=J26", "FAST")
   PORT BANK0_DATA_C2 = CONN_BANK0_DATA_C2,   UCF_NET_STRING=("LOC=J28", "FAST")
   PORT BANK0_DATA_C3 = CONN_BANK0_DATA_C3,   UCF_NET_STRING=("LOC=K24", "FAST")
   PORT BANK0_DATA_C4 = CONN_BANK0_DATA_C4,   UCF_NET_STRING=("LOC=J27", "FAST")
   PORT BANK0_DATA_C5 = CONN_BANK0_DATA_C5,  UCF_NET_STRING=("LOC=K29", "FAST")
   PORT BANK0_DATA_C6 = CONN_BANK0_DATA_C6,   UCF_NET_STRING=("LOC=L25", "FAST")
   PORT BANK0_DATA_C7 = CONN_BANK0_DATA_C7,   UCF_NET_STRING=("LOC=L26", "FAST")

   PORT BANK0_DATA_D0 = CONN_BANK0_DATA_D0,  UCF_NET_STRING=("LOC=P30", "FAST")
   PORT BANK0_DATA_D1 = CONN_BANK0_DATA_D1,  UCF_NET_STRING=("LOC=P23", "FAST")
   PORT BANK0_DATA_D2 = CONN_BANK0_DATA_D2,  UCF_NET_STRING=("LOC=P27", "FAST")
   PORT BANK0_DATA_D3 = CONN_BANK0_DATA_D3,  UCF_NET_STRING=("LOC=T29", "FAST")
   PORT BANK0_DATA_D4 = CONN_BANK0_DATA_D4,  UCF_NET_STRING=("LOC=R24", "FAST")
   PORT BANK0_DATA_D5 = CONN_BANK0_DATA_D5,   UCF_NET_STRING=("LOC=R28", "FAST")
   PORT BANK0_DATA_D6 = CONN_BANK0_DATA_D6,   UCF_NET_STRING=("LOC=U30", "FAST")
   PORT BANK0_DATA_D7 = CONN_BANK0_DATA_D7,   UCF_NET_STRING=("LOC=T28", "FAST")

   PORT BANK0_WEND_Z = CONN_BANK0_WEND_Z, UCF_NET_STRING=("LOC=G29", "FAST")
   PORT BANK0_WENC_Z = CONN_BANK0_WENC_Z, UCF_NET_STRING=("LOC=F29", "FAST")
   PORT BANK0_WENB_Z = CONN_BANK0_WENB_Z, UCF_NET_STRING=("LOC=H24", "FAST")
   PORT BANK0_WENA_Z = CONN_BANK0_WENA_Z, UCF_NET_STRING=("LOC=J24", "FAST")
   PORT BANK0_WEN_Z = CONN_BANK0_WEN_Z, UCF_NET_STRING=("LOC=F26", "FAST")
   PORT BANK0_OEN_Z = CONN_BANK0_OEN_Z, UCF_NET_STRING=("LOC=F30", "FAST")
   PORT BANK0_CEN_Z = CONN_BANK0_CEN_Z, UCF_NET_STRING=("LOC=G26", "FAST")
   PORT BANK0_CLKEN_Z = CONN_BANK0_CLKEN_Z, UCF_NET_STRING=("LOC=G30", "FAST")
   PORT BANK0_ADV_LDZ = CONN_BANK0_ADV_LDZ, UCF_NET_STRING=("LOC=K23", "FAST")



  ### EMAC ###
  # 10/100 Ethernet MAC
  PORT PHY_SLW0   = phy_slew0,     UCF_NET_STRING=("LOC=G16")
  PORT PHY_SLW1   = phy_slew1,     UCF_NET_STRING=("LOC=C16")
#  PIN PHY_RESET  = phy_rst_n,     UCF_NET_STRING=("LOC=D21")
  PORT PHY_MDINT  = phy_mii_int_n, UCF_NET_STRING=("LOC=C21")
  PORT PHY_CRS    = phy_crs,       UCF_NET_STRING=("LOC=F20")
  PORT PHY_COL    = phy_col,       UCF_NET_STRING=("LOC=C23")
  PORT PHY_TXD3   = phy_tx_data_3, UCF_NET_STRING=("LOC=C22")
  PORT PHY_TXD2   = phy_tx_data_2, UCF_NET_STRING=("LOC=B20")
  PORT PHY_TXD1   = phy_tx_data_1, UCF_NET_STRING=("LOC=B21")
  PORT PHY_TXD0   = phy_tx_data_0, UCF_NET_STRING=("LOC=G20")
  PORT PHY_TX_EN  = phy_tx_en,     UCF_NET_STRING=("LOC=G19")
  PORT PHY_TX_CLK = phy_tx_clk,    UCF_NET_STRING=("LOC=H16")
  PORT PHY_TX_ER  = phy_tx_er,     UCF_NET_STRING=("LOC=D21")
  PORT PHY_RX_ER  = phy_rx_er,     UCF_NET_STRING=("LOC=D22")
  PORT PHY_RX_CLK = phy_rx_clk,    UCF_NET_STRING=("LOC=C17")
  PORT PHY_RX_DV  = phy_dv,        UCF_NET_STRING=("LOC=B17")
  PORT PHY_RXD0   = phy_rx_data_0, UCF_NET_STRING=("LOC=B16")
  PORT PHY_RXD1   = phy_rx_data_1, UCF_NET_STRING=("LOC=F17")
  PORT PHY_RXD2   = phy_rx_data_2, UCF_NET_STRING=("LOC=F16")
  PORT PHY_RXD3   = phy_rx_data_3, UCF_NET_STRING=("LOC=D16")
  PORT PHY_MDC    = phy_mii_clk,   UCF_NET_STRING=("LOC=D17")
  PORT PHY_MDIO   = phy_mii_data,  UCF_NET_STRING=("LOC=A17")
 
END