These are instructions to modify the MPMC timing parameters so that they will work with the KVR266X64C25/512 512 MB memory DIMMs on the XUP Virtex-II Pro boards. 1) Generate your system using the base system builder and be sure to include the MPMC. (if you already have a system built with an MPMC which is giving bad reads then you can skip this step. 2) open your system.mhs file and replace the lines PORT fpga_0_DDR_SDRAM_DDR_CE_pin = fpga_0_DDR_SDRAM_DDR_CE, DIR = O PORT fpga_0_DDR_SDRAM_DDR_CS_n_pin = fpga_0_DDR_SDRAM_DDR_CS_n, DIR = O with PORT fpga_0_DDR_SDRAM_DDR_CE_pin = fpga_0_DDR_SDRAM_DDR_CE, DIR = O, VEC = [1:0] PORT fpga_0_DDR_SDRAM_DDR_CS_n_pin = fpga_0_DDR_SDRAM_DDR_CS_n, DIR = O, VEC = [1:0] 3) also in your system.mhs file replace BEGIN mpmc ... END with BEGIN mpmc PARAMETER INSTANCE = DDR_SDRAM PARAMETER HW_VER = 4.03.a PARAMETER C_MEM_PARTNO = CUSTOM PARAMETER C_MEM_TYPE = DDR PARAMETER C_USE_STATIC_PHY = 1 PARAMETER C_MEM_CLK_WIDTH = 3 PARAMETER C_STATIC_PHY_RDEN_DELAY = 6 PARAMETER C_MPMC_CLK0_PERIOD_PS = 10000 PARAMETER C_MPMC_BASEADDR = 0xA0000000 PARAMETER C_MPMC_HIGHADDR = 0xBFFFFFFF PARAMETER C_MPMC_CTRL_BASEADDR = 0x84800000 PARAMETER C_MPMC_CTRL_HIGHADDR = 0x8480ffff PARAMETER C_MEM_NUM_RANKS = 2 PARAMETER C_MEM_PART_DATA_DEPTH = 32 PARAMETER C_MEM_PART_DATA_WIDTH = 64 PARAMETER C_MEM_PART_NUM_COL_BITS = 10 PARAMETER C_MEM_PART_CAS_A_FMAX = 133 PARAMETER C_MEM_PART_CAS_A = 2.5 PARAMETER C_MEM_PART_TRAS = 60000 PARAMETER C_MEM_PART_TRASMAX = 120000000 PARAMETER C_MEM_PART_TRC = 90000 PARAMETER C_MEM_PART_TWR = 20000 PARAMETER C_MEM_PART_TRRD = 20000 PARAMETER C_MEM_PART_TRCD = 30000 PARAMETER C_MEM_PART_TREFI = 7800000 PARAMETER C_MEM_PART_TRFC = 100000 PARAMETER C_MEM_PART_TRP = 30000 PARAMETER C_MEM_CS_N_WIDTH = 2 PARAMETER C_MEM_CE_WIDTH = 2 BUS_INTERFACE SPLB0 = mb_plb BUS_INTERFACE MPMC_CTRL = mb_plb PORT DDR_Addr = fpga_0_DDR_SDRAM_DDR_Addr PORT DDR_BankAddr = fpga_0_DDR_SDRAM_DDR_BankAddr PORT DDR_CAS_n = fpga_0_DDR_SDRAM_DDR_CAS_n PORT DDR_CE = fpga_0_DDR_SDRAM_DDR_CE PORT DDR_CS_n = fpga_0_DDR_SDRAM_DDR_CS_n PORT DDR_RAS_n = fpga_0_DDR_SDRAM_DDR_RAS_n PORT DDR_WE_n = fpga_0_DDR_SDRAM_DDR_WE_n PORT DDR_DM = fpga_0_DDR_SDRAM_DDR_DM PORT DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS PORT DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ PORT DDR_Clk = fpga_0_DDR_SDRAM_DDR_Clk PORT DDR_Clk_n = fpga_0_DDR_SDRAM_DDR_Clk_n PORT MPMC_Clk0 = sys_clk_s PORT MPMC_Clk90 = DDR_SDRAM_mpmc_clk_90_s PORT MPMC_Clk_Mem = DDR_SDRAM_MPMC_Clk_Mem PORT MPMC_Rst = sys_periph_reset END 4) Finally in your UCF file replace the lines Net fpga_0_DDR_SDRAM_DDR_CE_pin LOC=R26; Net fpga_0_DDR_SDRAM_DDR_CE_pin IOSTANDARD = SSTL2_II; Net fpga_0_DDR_SDRAM_DDR_CS_n_pin LOC=R24; Net fpga_0_DDR_SDRAM_DDR_CS_n_pin IOSTANDARD = SSTL2_II; with Net fpga_0_DDR_SDRAM_DDR_CE_pin<0> LOC=R26; Net fpga_0_DDR_SDRAM_DDR_CE_pin<0> IOSTANDARD = SSTL2_II; Net fpga_0_DDR_SDRAM_DDR_CE_pin<1> LOC=R25; Net fpga_0_DDR_SDRAM_DDR_CE_pin<1> IOSTANDARD = SSTL2_II; Net fpga_0_DDR_SDRAM_DDR_CS_n_pin<0> LOC=R24; Net fpga_0_DDR_SDRAM_DDR_CS_n_pin<0> IOSTANDARD = SSTL2_II; Net fpga_0_DDR_SDRAM_DDR_CS_n_pin<1> LOC=R23; Net fpga_0_DDR_SDRAM_DDR_CS_n_pin<1> IOSTANDARD = SSTL2_II; ***NOTE*** This will change the address range of the ddr memory to 0xA0000000 - 0xBFFFFFFF, if you would like to change this the first hex number of the start address must be divisible by 2... ie the memory must start at 0x60000000, 0x80000000, 0xA0000000, etc. So adjust your addresses appropriately. With regards to making this the default, it seems that the only reason the 256mb module (KVR266x64C25/256) was used was that that model was included from xilinx by default in the mpmc. The 512 mb module (KVR266X64C25/512) was not included by xilinx and apparently has slightly different timing. One thing I could try doing is modify the xbd board file to include both the 512mb and the 256mb options which the user can choose between during the base system builder. I'm not sure exactly how to do it or if it will work but I could try if you'd like. David