These modules have evolved from a set of labs used at an EDK workshop given at the University of Toronto in November 2003. For versions 6.3i and lower, the hardware platform is the Xilinx Multimedia board. Starting with 8.2i we include the Xilinx XUPV2P board. For version 10.1i, we are only supporting the Xilinx XUPV2P board. All instructions are tuned to our lab environment.
The modules are grouped according to the ISE and EDK tools versions.
The 10.1 tools are the last to support the Virtex device on the Xilinx XUPV2P board. Any references in these modules to the Xilinx Multimedia board have not been tested with this version of the tools.
| Description | Other Files | |
| Tips.pdf | A collection of troubleshooting tips based on frustrating experiences! If you have anything to add, please pass it on. This version is still from 6.3i but most of it is still relevant. | |
| m00.pdf | A guide to installing and configuring ISE, EDK, ChipScope, Modelsim and the Modelsim libraries. | |
| m01.pdf | Build a basic MicroBlaze system and an intro to the design environment. | m01.zip |
| m02.pdf | Adding IP to the MicroBlaze system of Module 1 and an intro to device drivers. | m02.zip |
| m03.pdf | Adding a timer to the Module 2 system. Using device drivers with interrupts. Please see the note about using GDB | m03.zip |
| m04.pdf | Using a PLB ethernet MAC peripheral on a MicroBlaze. Adds
to the design in Module 3. You can't really do much to test
this lab as there is no longer any loopback functionality in
the ethernet MAC core for this version. The exercise will
show you how to connect a more complex core.
If you are brave, you can try connecting to the board of another group and see if you can send packets through. If you actually get this to work please write it up and we'll add it to this module! Note, you'll need to connect through a switch or a crossover cable. |
|
| m05.pdf | Adding a user-designed core to a MicroBlaze system without using the Create/Import Peripheral Wizard. The zip file link goes directly to the SFU version. Professor Shannon is the original creator. | m05.zip |
| m06.pdf | A really quick start to ISE, the tools for doing basic Xilinx FPGA hardware design. More about ISE can be found here. This module also touches CoreGen, memory initialization and iMPACT for downloading. | m06.zip |
| m07.pdf | A quick intro to the ModelSim HDL simulator in a Xilinx environment. | m07.zip |
| m10.pdf | Using the FSLs. A guide through xapp529 and finding other related documentation. The zip file is an updated version of the version that goes with the app note and has been adapted to work here. | xapp529.pdf, m10.zip |
| m16.pdf | Building a multi-MicroBlaze system using the Multi-Ported Memory Controller (MPMC) | |
| m17.pdf | A quick tutorial on using ChipScope | chipscope.c |
The 10.1 tools are the last to support the Virtex device on the Xilinx XUPV2P board. Any references in these modules to the Xilinx Multimedia board have not been tested with this version of the tools.
| Description | Other Files | |
| Tips.pdf | A collection of troubleshooting tips based on frustrating experiences! If you have anything to add, please pass it on. This version is still from 6.3i but most of it is still relevant. | |
| m01.pdf | Build a basic MicroBlaze system and an intro to the design environment. | m01.zip |
| m02.pdf | Adding IP to the MicroBlaze system of Module 1 and an intro to device drivers. | m02.zip |
| m03.pdf | Adding a timer to the Module 2 system. Using device drivers with interrupts. Please see the note about using GDB | m03.zip |
| m04.pdf | Using a PLB ethernet MAC peripheral on a MicroBlaze. Adds
to the design in Module 3. You can't really do much to test
this lab as there is no longer any loopback functionality in
the ethernet MAC core for this version. The exercise will
show you how to connect a more complex core.
If you are brave, you can try connecting to the board of another group and see if you can send packets through. If you actually get this to work please write it up and we'll add it to this module! Note, you'll need to connect through a switch or a crossover cable. |
|
| m05.pdf | Adding a user-designed core to a MicroBlaze system without using the Create/Import Peripheral Wizard. The zip file link goes directly to the SFU version. Professor Shannon is the original creator. | m05.zip |
| m06.pdf | A really quick start to ISE, the tools for doing basic Xilinx FPGA hardware design. More about ISE can be found here. This module also touches CoreGen, memory initialization and iMPACT for downloading. | m06.zip |
| m07.pdf | A quick intro to the ModelSim HDL simulator in a Xilinx environment. | m07.zip |
| m10.pdf | Using the FSLs. A guide through xapp529 and finding other related documentation. The zip file is an updated version of the version that goes with the app note and has been adapted to work here. | xapp529.pdf, m10.zip |
| m16.pdf | Building a multi-MicroBlaze system using the Multi-Ported Memory Controller (MPMC) | |
| m17.pdf | A quick tutorial on using ChipScope | chipscope.c |
| Description | Other Files | |
| Tips.pdf | A collection of troubleshooting tips based on frustrating experiences! If you have anything to add, please pass it on. This version is still from 6.3i but most of it is still relevant. | |
| m01.pdf | Build a basic MicroBlaze system and an intro to the design environment. | m01.zip |
| m02.pdf | Adding IP to the MicroBlaze system of Module 1 and an intro to device drivers. | m02.zip |
| m03.pdf | Adding a timer to the Module 2 system. Using device drivers with interrupts. Please see the note about using GDB | m03.zip |
| m04.pdf | Using an OPB ethernet MAC peripheral on a MicroBlaze. Adds to the design in Module 3. | |
| m05.pdf | Adding a user-designed core to a MicroBlaze system without using the Create/Import Peripheral Wizard. | m05.zip |
| m06.pdf | A really quick start to ISE, the tools for doing basic Xilinx FPGA hardware design. More about ISE can be found here. This module also touches CoreGen, memory initialization, iMPACT for downloading and the pushbuttons on the Multimedia board. It also gets those blinking LEDs to stop blinking! | m06.zip |
| m07.pdf | A quick intro to the ModelSim HDL simulator in a Xilinx environment. | m07.zip |
| m08.pdf | Connecting to the ZBT memory on the Multimedia board using
the OPB bus. This shows how to connect one memory and all
five memories.
A behavioural model of the ZBT memory chip is included in the m08.zip file. |
m08.zip |
| m10.pdf | Using the FSLs. A guide through xapp529 and finding other related documentation. The zip file is an updated version of the version that goes with the app note and has been adapted to work here. | xapp529.pdf, m10.zip |
| Description | Other Files | |
| Tips.pdf | A collection of troubleshooting tips based on frustrating experiences! If you have anything to add, please pass it on. | |
| m01.pdf | Build a basic MicroBlaze system and an intro to the design environment. | m01.zip |
| m02.pdf | Adding IP to the MicroBlaze system of Module 1 and an intro to device drivers. | Uses m01.zip from above. |
| m03.pdf | Adding a timer to the Module 2 system. Using device drivers with interrupts. Please see the note about using GDB | Uses m01.zip from above. |
| m04.pdf | Using an OPB ethernet MAC peripheral on a MicroBlaze. Adds to the design in Module 3. | m04.zip |
| m05.pdf | Adding a user-designed core to a MicroBlaze system without using the Create/Import Peripheral Wizard. | m05.zip |
| m06.pdf | A really quick start to ISE, the tools for doing basic Xilinx FPGA hardware design. More about ISE can be found here. This module also touches CoreGen, memory initialization, iMPACT for downloading and the pushbuttons on the Multimedia board. It also gets those blinking LEDs to stop blinking! | m06.zip |
| m07.pdf | A quick intro to the ModelSim HDL simulator in a Xilinx environment. This has been improved significantly from the 6.2i version. | |
| m08.pdf | Connecting to the ZBT memory on the Multimedia board using
the OPB bus. This shows how to connect one memory and all
five memories.
A behavioural model of the ZBT memory chip is included in the m08.zip file. |
m08.zip |
| ZBT | Example 50MHz and 100MHz ZBT memory designs using the EMC controller. A DCM configuration different from the one in m08 is used. See the DCM configurations figures. | 50MHz, 100MHz, DCM configurations |
| ZBT | Standalone ZBT memory controller. Use these blocks if you do not want to interface to the OPB bus. This Verilog core has been successfully used in designs on the Multimedia board. It is a modified version of the core available as ZBT RAM Memory Controller in the Multimedia Board Design Examples. It might be wise to look at the original version. | Verilog ZBT core |
| ZBT | There is also another core with both Verilog and VHDL versions available on the Xilinx web site. The appnote xapp136 is informative, even if you do not use this core. A version is available here but check the web site for updates. | xapp136, VHDL, Verilog |
| m10.pdf | Using the FSLs. A guide through xapp529 and finding other related documentation. The zip file is an updated version of the version that goes with the app note and has been adapted to the Multimedia boards. | xapp529.pdf, m10.zip |
| m13.pdf | An MP3 player that works on the Multimedia board. We adopted this design, but didn't create it. We kinda try to keep it working on the board, but we can't guarantee support. This uses some custom IP cores that could conceivably be replaced by new cores that are now available if someone wanted to try. See the document for more details. | m13.zip |
| Description | Other Files | |
| Tips.pdf | A collection of troubleshooting tips based on frustrating experiences! | |
| m01.pdf | Build a basic MicroBlaze system and an intro to the design environment. | lab1.zip |
| m02.pdf | Adding IP to the MicroBlaze system of Module 1 and an intro to device drivers. | Uses lab1.zip from above. |
| m03.pdf | Adding a timer to the Module 2 system. Using device drivers with interrupts. | Uses lab1.zip from above. |
| m04.pdf | Using an OPB ethernet MAC peripheral on a MicroBlaze. Adds to the design in Module 3. | lab4.zip |
| m05.pdf | Adding a user-designed core to a MicroBlaze system. | m05.zip |
| m06.pdf | A really quick start to ISE, the tools for doing basic Xilinx FPGA hardware design. More about ISE can be found here. This module also touches CoreGen, memory initialization, iMPACT for downloading and the pushbuttons on the Multimedia board. It also gets those blinking LEDs to stop blinking! | m06.zip |
| m07.pdf | A quick intro to the ModelSim HDL simulator in a Xilinx environment. There is a free ModelSim Xilinx Edition available. At that link, you should start with the recommended link for first timers. | |
| m08.pdf | Using the ZBT memory on the Multimedia board. | m08.zip |
| m09.pdf | Integrating a Verilog design into a MicroBlaze System. Includes building and modelling an OPB interface. You will need the IBM CoreConnect Toolkit. To get it from Xilinx, you will need to first agree to a license. | |
| m10.pdf | Using the FSLs. A guide through xapp529 and finding other related documentation. | xapp529.pdf, xapp529_6_2.zip |
| m12.pdf | A quick starter for using ChipScope. | |
| m13.pdf | An MP3 player that works on the Multimedia board. We adopted this design, but didn't create it. We kinda try to keep it working on the board, but we can't guarantee support. | m13.zip |
| m14.pdf | A MicroBlaze TFTP server. | m14.zip |
| Description | Other Files | |
| Lab 1.pdf | Build a basic MicroBlaze system and an intro to the design environment. | lab1.zip |
| Lab 2.pdf | Adding IP to the MicroBlaze system of Lab 1 and an intro to device drivers. | lab1.zip |
| Lab 3.pdf | Adding a timer to the Lab 2 system. Using device drivers with interrupts. | |
| Lab 4.pdf | Using an OPB ethernet MAC peripheral on a MicroBlaze. Adds to the design in Lab 3. | lab4.zip |
| Lab 4.5.pdf | Adding a user-designed core to a MicroBlaze system. | lab4.5.zip |