Library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;


entity multiply is
	port(
	clock:	in STD_LOGIC;
	ready:	in STD_LOGIC;
	done:		out STD_LOGIC;
	arg0:		in STD_LOGIC_VECTOR (7 downto 0);
	arg1:		in STD_LOGIC_VECTOR (7 downto 0);
	result:	out STD_LOGIC_VECTOR (15 downto 0)

	);
end multiply;

architecture RTL of multiply is
	signal 	inport1:	STD_LOGIC_VECTOR (7 downto 0):="00000000";
	signal 	inport2:	STD_LOGIC_VECTOR (7 downto 0):="00000000";

	signal	mult1:	STD_LOGIC_VECTOR (7 downto 0):="00000000";
	signal	mult2:	STD_LOGIC_VECTOR (8 downto 0):="000000000";

	signal	product:	STD_LOGIC_VECTOR (15 downto 0):="0000000000000000";
	signal	outport:	STD_LOGIC_VECTOR (15 downto 0):="0000000000000000";

	signal	clk:		STD_LOGIC:='0';
	signal 	go:		STD_LOGIC:='0';

	signal	complete:	STD_LOGIC:='0';
	signal	count:	STD_LOGIC_VECTOR (2 downto 0):="000";
	signal	bitpair:	STD_LOGIC_VECTOR (2 downto 0):="000";


begin
	clk 		<= clock;
	go		<= ready ;
	
	inport1	<= arg0;	--multiplicand
	inport2	<= arg1;	-- multiplier

	done 		<= complete;
	result	<= outport;
	bitpair (2 downto 0) <= mult2 (2 downto 0);



MAIN_PROCESS: process (clk,go,complete,count,inport1,inport2)
variable prodvar: STD_LOGIC_VECTOR (15 downto 0):="0000000000000000";
begin
	if (clk'event and clk = '1') then
		if (complete = '1' and go = '1') then
			complete <= '0';	
			mult1 <= inport1;
			mult2 (8 downto 1) <= inport2 (7 downto 0);
			mult2(0) <= '0';
			prodvar := "0000000000000000";
			count <= "000";
		elsif (complete = '0' and not(count = "100")) then
			prodvar := product;
			-- Cases 000 and 111 are 0 and are ignored
			if (bitpair = "001" or bitpair = "010") then
				prodvar := prodvar + mult1;
			elsif	(bitpair = "011") then
				prodvar := prodvar + std_logic_vector((shl(unsigned(mult1),"01")));
			elsif	(bitpair = "100") then
				prodvar := prodvar - std_logic_vector((shl(unsigned(mult1),"01")));

			elsif (bitpair = "101" or bitpair = "110") then
				prodvar := prodvar - mult1;
			end if;
			
			prodvar := std_logic_vector(shl(unsigned(prodvar), "10"));
			mult2 <= std_logic_vector(shr(unsigned(mult2),
"10"));
			count <= count + '1';
			product <= prodvar;
		elsif (count = "100" and complete = '0') then
			complete <= '1';
			outport <= product;
	
		end if;
	end if;
end process;

end RTL;