library IEEE;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_booth.all;

entity booth_DW01_addsub_10_0 is

   port( A, B : in std_logic_vector (0 to 9);  CI, ADD_SUB : in std_logic;  SUM
         : out std_logic_vector (0 to 9);  CO : out std_logic);

end booth_DW01_addsub_10_0;

architecture SYN_rpl of booth_DW01_addsub_10_0 is

   component ND2
      port( A, B : in std_logic;  Z : out std_logic);
   end component;
   
   component NR2
      port( A, B : in std_logic;  Z : out std_logic);
   end component;
   
   component OR2
      port( A, B : in std_logic;  Z : out std_logic);
   end component;
   
   component AO5
      port( A, B, C : in std_logic;  Z : out std_logic);
   end component;
   
   component EO1
      port( A, B, C, D : in std_logic;  Z : out std_logic);
   end component;
   
   component EO
      port( A, B : in std_logic;  Z : out std_logic);
   end component;
   
   component IV
      port( A : in std_logic;  Z : out std_logic);
   end component;
   
   component EON1
      port( A, B, C, D : in std_logic;  Z : out std_logic);
   end component;
   
   component AO2
      port( A, B, C, D : in std_logic;  Z : out std_logic);
   end component;
   
   component EN
      port( A, B : in std_logic;  Z : out std_logic);
   end component;
   
   signal n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16
      , n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, 
      n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44 : 
      std_logic;

begin
   
   U1 : ND2 port map( A => n2, B => n3, Z => n1);
   U2 : NR2 port map( A => A(8), B => n5, Z => n4);
   U3 : OR2 port map( A => A(7), B => n7, Z => n6);
   U4 : ND2 port map( A => n9, B => n10, Z => n8);
   U5 : ND2 port map( A => n12, B => n13, Z => n11);
   U6 : NR2 port map( A => A(4), B => n15, Z => n14);
   U7 : NR2 port map( A => A(3), B => n17, Z => n16);
   U8 : OR2 port map( A => A(2), B => n19, Z => n18);
   U9 : AO5 port map( A => A(1), B => n21, C => n22, Z => n20);
   U10 : EO1 port map( A => B(9), B => ADD_SUB, C => B(9), D => ADD_SUB, Z => 
                           n23);
   U11 : EO1 port map( A => B(8), B => ADD_SUB, C => B(8), D => ADD_SUB, Z => 
                           n5);
   U12 : EO1 port map( A => B(7), B => ADD_SUB, C => B(7), D => ADD_SUB, Z => 
                           n24);
   U13 : EO1 port map( A => B(6), B => ADD_SUB, C => B(6), D => ADD_SUB, Z => 
                           n25);
   U14 : EO1 port map( A => B(5), B => ADD_SUB, C => B(5), D => ADD_SUB, Z => 
                           n26);
   U15 : EO1 port map( A => B(4), B => ADD_SUB, C => B(4), D => ADD_SUB, Z => 
                           n15);
   U16 : EO1 port map( A => B(3), B => ADD_SUB, C => B(3), D => ADD_SUB, Z => 
                           n17);
   U17 : EO1 port map( A => B(2), B => ADD_SUB, C => B(2), D => ADD_SUB, Z => 
                           n27);
   U18 : EO port map( A => n22, B => n28, Z => SUM(0));
   U19 : EO port map( A => n22, B => n29, Z => SUM(1));
   U20 : EO port map( A => n27, B => n30, Z => SUM(2));
   U21 : EO port map( A => n17, B => n31, Z => SUM(3));
   U22 : EO port map( A => n15, B => n32, Z => SUM(4));
   U23 : EO port map( A => n26, B => n33, Z => SUM(5));
   U24 : EO port map( A => n25, B => n34, Z => SUM(6));
   U25 : EO port map( A => n24, B => n35, Z => SUM(7));
   U26 : EO port map( A => n5, B => n36, Z => SUM(8));
   U27 : IV port map( A => ADD_SUB, Z => n2);
   U28 : EON1 port map( A => n37, B => n4, C => n5, D => A(8), Z => n7);
   U29 : AO2 port map( A => n7, B => A(7), C => n6, D => n24, Z => n10);
   U30 : AO2 port map( A => n38, B => A(6), C => n8, D => n25, Z => n13);
   U31 : EON1 port map( A => n39, B => n16, C => n17, D => A(3), Z => n19);
   U32 : AO2 port map( A => n2, B => n40, C => ADD_SUB, D => B(1), Z => n22);
   U33 : EO port map( A => n23, B => n41, Z => SUM(9));
   U34 : AO2 port map( A => n3, B => n2, C => A(9), D => ADD_SUB, Z => n41);
   U35 : AO2 port map( A => ADD_SUB, B => A(9), C => n1, D => n23, Z => n37);
   U36 : IV port map( A => n10, Z => n38);
   U37 : IV port map( A => n13, Z => n42);
   U38 : AO2 port map( A => n42, B => A(5), C => n11, D => n26, Z => n43);
   U39 : EO1 port map( A => n15, B => A(4), C => n43, D => n14, Z => n39);
   U40 : AO2 port map( A => n19, B => A(2), C => n18, D => n27, Z => n44);
   U41 : EN port map( A => A(0), B => n20, Z => n28);
   U42 : EO1 port map( A => A(1), B => n21, C => A(1), D => n21, Z => n29);
   U43 : EO port map( A => A(2), B => n19, Z => n30);
   U44 : EN port map( A => A(3), B => n39, Z => n31);
   U45 : EN port map( A => A(4), B => n43, Z => n32);
   U46 : AO2 port map( A => n12, B => n13, C => A(5), D => n42, Z => n33);
   U47 : AO2 port map( A => n9, B => n10, C => A(6), D => n38, Z => n34);
   U48 : EO port map( A => A(7), B => n7, Z => n35);
   U49 : EN port map( A => n37, B => A(8), Z => n36);
   U50 : IV port map( A => n44, Z => n21);
   U51 : IV port map( A => B(1), Z => n40);
   U52 : IV port map( A => A(5), Z => n12);
   U53 : IV port map( A => A(6), Z => n9);
   U54 : IV port map( A => A(9), Z => n3);

end SYN_rpl;