ECE1373S: VLSI Systems Design

Paul Chow

Spring 2005

HDL Examples

• Behavioural VHDL For a purely behavioural model.
• OK RTL VHDL Should synthesize to a reasonable circuit.
• Structural VHDL A Synopsys netlist of the adder resulting from synthesis of the above circuit.
• Bad VHDL for Synthesis This will not synthesize!
• Mealy FSM in Verilog Verilog example of a FSM that should synthesize okay.
• Moore FSM in Verilog Another Verilog example of a FSM that should synthesize okay.
• Design Example This is a simple example illustrating good design practices. You should study it and emulate it!

Notes and Handouts

• VHDL Slides by Sean Peng
• Pins to Verilog flow
• FPGA Design and Verification flow
• Custom and ASIC flows
• Sample directory structure
• progress.tex, progress.ps
• 505 Registers or Bust, a paper by Wilson Snyder
• Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs, a paper by Cliff Cummings
• Requirements and Report Format, report.tex

SystemC

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