Bibliography

1

Lesley Shannon and Paul Chow.
Standardizing the Performance Assessment of Reconfigurable Processor Architectures.
IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '03) Poster Session, April 2003.

2

Lesley Shannon and Paul Chow.
Leveraging Reconfigurability in the Design Process.
Microsystems Research and Development in Canada 2004 (MR&DCAN) TEXPO Poster, September 2004.
Winner of the CMC Componentware/CAD Award poster.pdf (138977) .

3

Lesley Shannon and Paul Chow.
Leveraging Reconfigurability in the Design Process.
IEEE International Conference on Field-Programmable Logic and Applications (FPL) PhD Forum poster, August 2005.
poster.pdf (59538) .

4

Lesley Shannon, Blair Fort, Arun Patel, Samir Parikh, Manuel Saldaña, and Paul Chow.
Designing an FPGA SoC using a Standardized IP Block Interface.
IEEE International Conference on Field-Programmable Technology (FPT) poster, December 2005.
poster.pdf (68291) .

5

Lesley Shannon and Paul Chow.
Using Reconfigurability to Achieve Real-Time Profiling for Hardware/Software Codesign.
In International Symposium on Field-Programmable Gate Arrays, pages 190-199. ACM, February 2004.
24/90 (27%) submissions accepted. paper.pdf (146510), poster.pdf (99013) .

6

Lesley Shannon and Paul Chow.
Maximizing System Performance: Using Reconfigurability to Monitor System Communications.
In International Conference on Field-Programmable Technology (FPT), pages 231-238, Brisbane, Australia, December 2004.
34/122 (28%) submissions accepted. paper.pdf (169860) .

7

Lesley Shannon and Paul Chow.
Simplifying the Integration of Processing Elements in Computing Systems using a Programmable Controller.
In IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05), pages 63-72, April 2005.
25/90 (28%) submissions accepted. paper.pdf (162539) .

8

Lesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, and Paul Chow.
A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification.
In IEEE International Conference on Field-Programmable Logic and Applications (FPL 2006), pages 289-294, August 2006.
85/307 (28%) full submissions accepted. paper.pdf (92869) .

9

Lesley Shannon and Paul Chow.
SIMPPL: An Adaptable SoC Framework using a Programmable Controller IP Interface to Facilitate Design Reuse.
IEEE Transactions on Very Large Scale Integration Systems, 15(4):377 - 390, April 2007.
paper.pdf (559017) .

10

Lesley Shannon.
Simplifying System-on-Chip Design through Architecture and System CAD Tools.
PhD thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, August 2006.

11

Tor Aamodt, Pedro Marcuello, Paul Chow, Antonio Gonzalez, Per Hammarlund, Hong Wang, and John P. Shen.
A Framework for Modeling and Optimization of Prescient Instruction Prefetch.
In SIGMETRICS '03, pages 13-24. ACM, June 2003.
Acceptance rate 12%. paper.pdf (444790) .

12

Tor M. Aamodt, Paul Chow, Per Hammarlund, Hong Wang, and John Shen.
Hardware Support for Prescient Instruction Prefetch.
In $10^{\mbox{th}}$ International Symposium on High-Performance Computer Architecture, pages 84-95. IEEE, February 2004.
27/153 (18%) submissions accepted. paper.pdf (479428) .

13

Tor M. Aamodt.
Modeling and Optimization of Speculative Threads.
PhD thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, October 2005.

14

Mazen A.R. Saghir, Paul Chow, and Corinna G. Lee.
Exploiting Dual Memory Banks in Digital Signal Processors.
In 1996 SIGARCH Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS VII), pages 234-243, Boston, MA, October 1996.
paper.ps.gz (54915) .

15

Mazen A.R. Saghir, Paul Chow, and Corinna G. Lee.
Automatic Data Partitioning for HLL DSP Compilers.
In The Sixth International Conference on Signal Processing Applications and Technology, ICSPAT'95, pages 866-871, Boston, MA, October 1995.
paper.ps.gz (28838) .

16

Mazen A.R. Saghir, Paul Chow, and Corinna G. Lee.
Towards Better DSP Architectures and Compilers.
In The Fifth International Conference on Signal Processing Applications and Technology, ICSPAT'94, pages 658-664, Dallas, Texas, October 1994.
paper.ps.gz (35626), .

17

Mazen A. R. Saghir, Paul Chow, and Corinna G. Lee.
A Comparison of Traditional and VLIW DSP Architectures for Compiled DSP Applications.
In International Workshop on Compiler and Architecture Support for Embedded Computing Systems-CASES'98, December 1998.
5 pages. paper.ps.gz (26100), slides.ps.gz (34271) .

18

Mazen A.R. Saghir.
Application-Specific Instruction-Set Architectures for Embedded DSP Applications.
PhD thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1998.
thesis.ps.gz (362850) .

19

Alex Kaganov, Daniel Nunes, Emanuel Ramalho, Arun Patel, Chris Madill, Manuel Saldaña, and Régis Pomès Paul Chow.
High-Performance Computing with Multi-FPGA Systems.
Microsystems Research and Development in Canada 2007 (MR&DCAN) TEXPO Poster, October 2007.
poster.pdf (11928037) .

20

Alexander Kaganov, Asif Lakhany, Paul Chow, and Alex Kreinin.
FPGA Acceleration of Monte-Carlo Based Credit Derivatives Pricing.
Eighth International Conference on Monte Carlo and Quasi-Monte Carlo Methods in Scientific Computing Poster Presentation, July 2008.

21

Manuel Saldaña, Daniel Nunes, Emanuel Ramalho, and Paul Chow.
Configuration and Programming of Heterogeneous Multiprocessors on a Multi-FPGA System Using TMD-MPI.
Microsystems Research and Development in Canada 2006 (MR&DCAN) TEXPO Poster, October 2006.
poster.pdf (13513807) .

22

Arun Patel, Christopher Madill, Manuel Saldaña, Christopher Comis, Dave Chui, Sam Lee, Régis Pomès, and Paul Chow.
Accelerating Biomolecular Simulation using a Scalable Network of Reconfigurable Hardware.
CMC Microsystems 2005 Annual Symposium TEXPO Poster, October 2005.
poster.pdf (6954902) .

23

Manuel Saldaña, Lesley Shannon, and Paul Chow.
The Routability of Multiprocessor Network Topologies in FPGAs.
International Symposium on Field-Programmable Gate Arrays poster, February 2006.
poster.pdf (4251046) .

24

Arun Patel, Christopher Madill, Manuel Saldaña, Christopher Comis, Régis Pomès, and Paul Chow.
A Scalable FPGA-based Multiprocessor.
In IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'06), pages 111-120, April 2006.
25/123 (20%) submissions accepted. paper.pdf (270858) .

25

Arun Patel.
A 3D Convolution Engine for Computing the Reciprocal Space Ewald Electrostatic Energy in Molecular Dynamics Simulations.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, January 2007.

26

Manuel Saldaña, Lesley Shannon, and Paul Chow.
The Routability of Multiprocessor Network Topologies in FPGAs.
In SLIP'06: International Workshop on System-Level Interconnect, pages 49-56. ACM/IEEE, March 2006.
paper.pdf (358305) .

27

Manuel Saldaña and Paul Chow.
TMD-MPI: An MPI Implementation for Multiple Processors across Multiple FPGAs.
In IEEE International Conference on Field-Programmable Logic and Applications (FPL 2006), pages 329-334, August 2006.
85/307 (28%) full submissions accepted. paper.pdf (155296) .

28

Manuel Saldaña, Daniel Nunes, Emanuel Ramalho, and Paul Chow.
Configuration and Programming of Heterogeneous Multiprocessors on a Multi-FPGA System Using TMD-MPI.
In 3rd International Conference on ReConFigurable Computing and FPGAs 2006 (ReConFig'06), September 2006.
8 pages. paper.pdf (666063) .

29

Manuel Saldaña, Lesley Shannon, Jia Shuo Yue, Sikang Bian, John Craig, and Paul Chow.
Routability of Network Topologies in FPGAs.
IEEE Transactions on Very Large Scale Integration Systems, 15(8):948 - 951, August 2007.
paper.pdf (624301) .

30

Manuel Saldaña.
A Parallel Programming Model for a Multi-FPGA Multiprocessor Machine.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, September 2006.

31

Christopher Comis.
A High-Speed Inter-Process Communication Architecture for FPGA-based Hardware Acceleration of Molecular Dynamics.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, September 2005.
thesis.pdf (731876), slides.ppt (3116032) .

32

David Chui.
An FPGA Implementation of the Ewald Direct Space and Lennard-Jones Compute Engines.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, September 2005.
thesis.pdf (1590128), slides.ppt (246272) .

33

Sam Lee.
An FPGA Implementation of the Smooth Particle Mesh Ewald Reciprocal Sum Compute Engine.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, September 2005.
thesis.pdf (1854548), slides.ppt (796160) .

34

Amy Wang.
Code Compaction for VLIW Instructions.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, September 2001.
thesis.ps.gz (350203) .

35

Lesley Lorraine Shannon.
Impact of Intellectual Property Cores on Field Programmable Gate Array Designs.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, December 2000.
thesis.ps.gz (371401), thesis.ps (2244154), thesis.pdf (939987) .

36

Juan Humberto Rico.
HDL-Level Partitioning of Circuits.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, December 2000.
thesis.ps.gz (599100) .

37

Jorge E. Carrillo E. and Paul Chow.
The Effect of Reconfigurable Units in Superscalar Processors.
In International Symposium on Field-Programmable Gate Arrays, pages 141-150. ACM, February 2001.
paper.ps (363276), paper.ps.gz (146728), paper.pdf (201396) .

38

Jorge Ernesto Carrillo Esparza.
Evaluation of the OneChip reconfigurable Processor.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, September 2000.
thesis.ps.gz (143442) .

39

Scott Nunweiler.
A Case Study in Design for Reuse Using VHDL.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1999.
thesis.ps.gz (628587) .

40

Jianghong Hu.
A Datapath Compiler with Technology Portability.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 2000.
thesis.ps.gz (854001), thesis.ps (7171262), thesis.pdf (2771258) .

41

Sean Peng.
UTDSP: A VLIW Programmable DSP Processor.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1999.
thesis.ps.gz (3706773), thesis.ps (5391879), thesis.pdf (8900402) .

42

Tor Aamodt and Paul Chow.
Numerical Error Minimizing Floating-Point to Fixed-Point ANSI C Compilation.
In 1st Workshop on Media Processors and DSPs (MPDSP-1 in conjunction with MICRO-32), pages 3-12, 1999.
paper.ps.gz (111792), paper.pdf (290065) .

43

Tor Aamodt and Paul Chow.
Embedded ISA Support for Enhanced Floating-Point to Fixed-Point ANSI C Compilation.
In International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES 2000), pages 128-137, November 2000.
paper.ps (998950), paper.ps.gz (155690), paper.pdf (396784), slides.ppt (1120768) .

44

Tor Aamodt, Andreas Moshovos, and Paul Chow.
The Predictability of Computations that Produce Unpredictable Outcomes.
In MTEAC-5 (in conjunction with MICRO-34), pages 23-34, 2001.
paper.pdf (192626) .

45

Tor Michael Aamodt.
Floating-Point to Fixed-Point Compilation and Embedded Architectural Support.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, January 2001.
thesis.ps.gz (642087) .

46

Tor M. Aamodt and Paul Chow.
Compile-Time and Instruction Set Methods for Improving Floating- to Fixed-Point Conversion Accuracy.
ACM Transactions on Embedded Computing Systems, 7(3):1-27, April 2008.
paper.pdf (730869) .

47

Jeffrey A. Jacob and Paul Chow.
Memory Interfacing and Instruction Specification for Reconfigurable Processors.
In International Symposium on Field-Programmable Gate Arrays, pages 145-154. ACM/SIGDA, February 1999.
paper.ps (811055), paper.ps.gz (236224), paper.pdf (95228) .

48

Jeffery A. Jacob.
Memory Interfacing for the OneChip Reconfigurable Processor.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1998.
thesis.ps.gz (645782) .

49

Vineet Chandra Joshi.
Using the Transmogrifier-2 to Prototype an ATM Wrap Sequencer.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1998.

50

Ralph D. Wittig and Paul Chow.
OneChip: An FPGA Processor With Reconfigurable Logic.
In The Fourth Annual IEEE Symposium on FPGAs for Custom Computing Machines FCCM'96, pages 126-135. IEEE, March 1996.
paper.ps (155887), paper.ps.gz (49472), paper.pdf (1059698), slides.ps.gz (29628) .

51

Ralph D. Wittig.
OneChip: An FPGA Processor With Reconfigurable Logic.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1995.
thesis.ps (509116), thesis.ps.gz (151124) .

52

David Yeh, Gennady Feygin, and Paul Chow.
RACER: A Reconfigurable Constraint-Length 14 Viterbi Decoder.
In The Fourth Annual IEEE Symposium on FPGAs for Custom Computing Machines FCCM'96, pages 60-69. IEEE, March 1996.
paper.ps (190678), paper.ps.gz (58685), paper.pdf (1059698), slides.ps.gz (196452) .

53

David Yeh, Paul Chow, and Gennady Feygin.
A Multiprocessor Viterbi Decoder Using Xilinx FPGAs.
In 1994 Canadian Workshop on Field-Programmable Devices, Kingston, Ontario, June 1994.
paper.ps.gz (44485) .

54

David Chun-Chin Yeh.
A Multiprocessor Viterbi Decoder Using Xilinx FPGAs.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1995.
thesis.ps.gz (196452) .

55

Mohamed El Ebiary.
History Guided Prefetching in a Telephone Switching Application.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1994.

56

Robert Jeschke.
An FPGA Based Reconfigurable Coprocessor for the IBM PC.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1994.

57

Harpreet Singh Gill.
Improved Optimization Strategies for Blocked Algorithms.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1994.

58

Pok Yan Lee.
An FPGA Implementation of the DLX.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1993.

59

Sushant Verman.
An FPGA-Based Reconfigurable Computing Array.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1993.

60

Mazen A.R. Saghir, Paul Chow, and Corinna G. Lee.
Application-Driven Design of DSP Architectures and Compilers.
In 1994 International Conference on Acoustics, Speech, and Signal Processing, pages II-437-II-440, Adelaide, Australia, April 1994. IEEE.
paper.pdf (347876) .

61

Mazen Saghir.
Architectural and Compiler Support for DSP Applications.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1993.

62

Vijaya Singh.
An Optimizing C Compiler for a General Purpose DSP Architecture.
Master's thesis, University of Toronto, Department of Electrical Engineering, Toronto, Ontario, M5S 3G4, 1992.

63

Qing Zheng and Paul Chow.
EXsim: A General Purpose Object-Oriented Environment for Discrete-Event Simulations.
In Object-Oriented Simulation Conference (OOS '93) of the 1993 Western Simulation MultiConference, pages 15-21, San Diego, January 1993.

64

Qing Zheng.
SEP: A General Purpose Object-Oriented Environment for Discrete-Event Simulations.
Master's thesis, University of Toronto, Department of Electrical Engineering, Toronto, Ontario, M5S 3G4, 1992.

65

Grant S. Goodes.
Stache: A Novel Cache Architecture Using Predictive Prefetch.
Master's thesis, University of Toronto, Department of Electrical Engineering, Toronto, Ontario, M5S 3G4, 1991.

66

Grant Goodes and Paul Chow.
A Methodology for Large Chip Design in the Cadence Edge Environment.
In CCVLSI'90, pages 6.8.1-6.8.8, Ottawa, October 1990.

67

Gennady Feygin, Paul Chow, P. Glenn Gulak, John Chappel, Grant Goodes, Oswin Hall, Ahmad Sayes, Satwant Singh, Michael B. Smith, and Steve Wilton.
A VLSI Implementation of a Cascade Viterbi Decoder with Traceback.
In 1993 IEEE International Symposium on Circuits and Systems, pages 1945-1948, May 1993.
paper.pdf (355733) .

68

Michael Takefman and Paul Chow.
A Streamlined DSP Microprocessor Architecture.
In International Conference on Acoustics, Speech, and Signal Processing, pages 1257-1260, Toronto, May 1991. IEEE.
paper.pdf (571448) .

69

Michael Takefman.
Improving the Performance of a DSP Microprocessor Architecture.
Master's thesis, University of Toronto, Department of Electrical Engineering, Toronto, Ontario, M5S 3G4, 1990.

70

Keith I. Farkas, Paul Chow, Norman P. Jouppi, and Zvonko Vranesic.
The Multicluster Architecture: Reducing Cycle Time Through Partitioning.
International Journal of Parallel Programming, 27(5):327-356, October 1999.

71

Keith Farkas, Paul Chow, Norman Jouppi, and Zvonko Vranesic.
The Multicluster Architecture: Reducing Cycle Time Through Partitioning.
In The 30th Annual International Symposium on Microarchitecture: MICRO-30, pages 149-159, Research Triangle Park, NC, December 1997. IEEE Computer Society/ACM.
paper.ps (250303), paper.ps.gz (60557), paper.pdf (92066) .

72

Keith I. Farkas, Paul Chow, Norman P. Jouppi, and Zvonko Vranesic.
Memory-System Design Considerations for Dynamically-Scheduled Processors.
In The 24th Annual International Symposium on Computer Architecture, pages 133-143. IEEE/ACM, June 1997.
An extended version is available as WRL Research Report 97/1. paper.ps (684713), paper.ps.gz (98279), paper.pdf (160092), Report 97/1 .

73

Keith I. Farkas, Norman P. Jouppi, and Paul Chow.
Register File Design Configurations in Dynamically Scheduled Processors.
In The 2nd International Symposium on High-Performance Computer Architecture, pages 40-51. IEEE, February 1996.
Also available as WRL Research Report 95/10. paper.ps (449232), paper.ps.gz (86453), paper.pdf (125672), Report 95/10 .

74

Keith I. Farkas, Norman P. Jouppi, and Paul Chow.
How Useful are Non-blocking Loads, Stream Buffers, and Speculative Execution in Multiple Issue Processors?
In First International Symposium on High-Performance Computer Architecture, pages 78-89. IEEE/ACM, January 1995.
Also available as WRL Research Report 94/8. paper.pdf (850409), Report 94/8 .

75

Keith Istvan Farkas.
Memory-system Design Considerations for Dynamically-Scheduled Microprocessors.
PhD thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1997.
thesis.ps (3086589), thesis.ps.gz (551790) .

76

Dean D'Mello.
Synthesis of FPAA Cores Using an Intermediate Language Layout Language Approach.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1996.

77

Gennady Feygin, P. Glenn Gulak, and Paul Chow.
Minimizing Excess Code Length and VLSI Complexity in the Multiplication Free Approximation of Arithmetic Coding.
Journal of Information Processing and Management: Special Issue on Data Compression, 30(6):805-816, 1994.

78

Gennady Feygin, P. Glenn Gulak, and Paul Chow.
Architectural Advances in the VLSI Implementation of Arithmetic Coding for Binary Image Compression.
In Data Compression Conference DCC '94, pages 254-263. IEEE, March 1994.
paper.pdf (443679) .

79

Gennady Feygin, P. Glenn Gulak, and Paul Chow.
Minimizing Error and VLSI Complexity in the Multiplication Free Approximation of Arithmetic Coding.
In Data Compression Conference DCC '93, pages 118-127. IEEE, March 1993.
paper.pdf (387990) .

80

Gennady Feygin.
Arithmetic Coding: Algorithms and VLSI Architectures.
PhD thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1995.
Co-supervised with Glenn Gulak.

81

Paul Chow, Paul Chow, and P. Glenn Gulak.
A Field-Programmable Mixed-Analog-Digital Array.
In 1995 International Symposium on Field-Programmable Arrays, pages 104-109. ACM/SIGDA, February 1995.
paper.pdf (113781) .

82

Paul Chow.
A Field-Programmable Mixed-Analog-Digital Array.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1994.
Co-supervised with Glenn Gulak, thesis.ps.gz (204218) .

83

Paul Chow, Soon Ong Seo, Jonathan Rose, Kevin Chung, Gerard Páez-Monzón, and Immanuel Rahardja.
The Design of an SRAM-Based Field-Programmable Gate Array, Part I: Architecture.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 7(2):191-197, June 1999.
paper.pdf (178930) .

84

Paul Chow, Soon Ong Seo, Jonathan Rose, Kevin Chung, Gerard Páez-Monzón, and Immanuel Rahardja.
The Design of an SRAM-Based Field-Programmable Gate Array, Part II: Circuit Design and Layout.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 7(3):321-330, September 1999.
paper.pdf (528590) .

85

Paul Chow, Soon Ong Seo, Kevin Chung, Gerard Paez, and Jonathan Rose.
A High-Speed FPGA Using Programmable Mini-tiles.
In Symposium on Integrated Systems, previously the Conference on Advanced Research in VLSI, pages 103-122, March 1993.
paper.ps (664109), paper.ps.gz (101397) .

86

Satwant Singh, Jonathan Rose, David Lewis, Kevin Chung, and Paul Chow.
Optimization of Field-Programmable Gate Array Logic Block Architecture for Speed.
In Custom Integrated Circuits Conference, pages 6.1.1-6.1.6. IEEE, May 1991.
paper.pdf (409783) .

87

Kevin Chung, Satwant Singh, Jonathan Rose, and Paul Chow.
Using Hierarchical Logic Blocks to Improve the Speed of Field-Programmable Gate Arrays.
In Will Moore and Wayne Luk, editors, FPGAs, chapter 3.3, pages 103-113. Abingdon EE&CS Books, 15 Harcourt Way, Abingdon OX14 1NV, England, 1991.
Presented at the Oxford 1991 International Workshop on Field Programmable Logic and Applications.

88

Satwant Singh, Jonathan Rose, Paul Chow, and David Lewis.
The Effect of Logic Block Architecture on FPGA Performance.
IEEE Journal of Solid-State Circuits, 27(3):281-287, March 1992.
paper.pdf (724665) .

89

Satwant Singh.
The Effect of Logic Block Architecture on the Speed of Field-Programmable Gate Arrays.
Master's thesis, University of Toronto, Department of Electrical Engineering, Toronto, Ontario, M5S 3G4, 1991.
Co-supervised with Jonathan Rose.

90

Gennady Feygin, Patrick Glenn Gulak, and Paul Chow.
A Multiprocessor Architecture for Viterbi Decoders with Linear Speed-Up.
IEEE Transactions on Signal Processing, 41(9):2907-2917, September 1993.
paper.pdf (960806) .

91

Gennady Feygin, Patrick Glenn Gulak, and Paul Chow.
Generalized Cascade Viterbi Decoder--A Locally Connected Multiprocessor with Linear Speed-Up.
In International Conference on Acoustics, Speech, and Signal Processing, pages 1097-1100, Toronto, May 1991.
paper.pdf (612785) .