OneChip is a reconfigurable processor developed in Department of Electrical and Computer Engineering at the University of Toronto. It is a third generation architecture that integrates a Reconfigurable Functional Unit (RFU) into a superscalar Reduced Instruction Set Computer (RISC) processor's pipeline. The architecture allows dynamic scheduling and dynamic reconfiguration. It also provides support for pre-loading configurations and for Least Recently Used (LRU) configuration management.

What is a reconfigurable processor? It is the combination of a general purpose processor (such as a MIPS) and reconfigurable logic (such as an FPGA). The OneChip Project goal is to investigate how these two technologies can be interfaced to speed up applications.

OneChip is designed to speed up applications by optimizing instructions at the loop-level. By targeting coarse-grain instructions in a program, one can generate a specialized hardware to implement in the RFU and replace them in the program. Furthermore, since the RFU in OneChip has access to memory, it acts as a specialized coprocessor. This allows the processor to speed up streamming applications (i.e. those that perform the same operations to big blocks of data) such as multimedia or DSP-type.

To evaluate the performance of the OneChip architecture, we have compiled and executed several off-the-shelf software applications on Sim-OneChip. By comparing the architecture to a similar one but without dynamic scheduling and without an RFU, OneChip achieves a performance improvement and shows a speedup range from 2.16 up to 32 for different applications and data sizes.

Sim-OneChip

Sim-OneChip 1.0 is available for non-commercial research purposes. You can download the simulator from:

• sim-onechip-1.0.tar.gz
  [ ftp ]

People

• Faculty
  • Paul Chow
• Former graduate students
  • Jorge E. Carrillo
  • Jeffrey A. Jacob
  • Ralph D. Wittig

Research Links

• SimpleScalar Tools Home Page
• MediaBench Home
• SPEC Home
• FPGA Conference Proceedings
• FCCM Conference Proceedings
• FPL Conference Proceedings

Acknowledgements

Publications

• Jorge E. Carrillo E. and Paul Chow. "The Effect of Reconfigurable Units in Superscalar Processors". In Ninth ACM International Symposium on Field-Programmable Gate Arrays (FPGA'01), pages 141-150. ACM/SIGDA, February 2001.
  [ ps | ps.gz | pdf ]

• Jorge E. Carrillo E. Evaluation of the OneChip Reconfigurable Processor. Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 2000.
  [ ps.gz | pdf ]

• Jeffrey A. Jacob and Paul Chow. "Memory Interfacing and Instruction Specification for Reconfigurable Processors". In International Symposium on Field-Programmable Gate Arrays (FPGA'99), pages 145-154. ACM/SIGDA, February 1999.
  [ ps | ps.gz | pdf ]

• Jeffrey A. Jacob. Memory Interfacing for the OneChip Reconfigurable Processor. Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1998.
  [ ps.gz ]

• Ralph D. Wittig and Paul Chow. "OneChip: An FPGA Processor With Reconfigurable Logic". In The Fourth Annual IEEE Symposium on FPGAs for Custom Computing Machines (FCCM'96), pages 126-135. IEEE, March 1996.
  [ ps | ps.gz | pdf ]

• Ralph D. Wittig. OneChip: An FPGA Processor With Reconfigurable Logic. Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1995.
  [ ps.gz ]