Complete Publication and Completed Student Thesis List

 

This is a chronological list of all publications and student theses that have been completed.

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Refereed Journal Publications

1

Manuel Saldaña, Arun Patel, Hao Jun Liu, and Paul Chow.
Using Partial Reconfiguration and Message Passing to Enable FPGA-Based Generic Computing Platforms.
International Journal of Reconfigurable Computing, vol. 2012, 2012.
Article ID 127302, 10 pages, doi:10.1155/2012/127302 Online link

2

Lesley Shannon and Paul Chow.
Leveraging Reconfigurability in the Hardware/Software Codesign Process.
ACM Transactions on Reconfigurable Technology and Systems, 4(3):28:1-28:27, August 2011.

3

Alexander Kaganov, Asif Lakhany, and Paul Chow.
FPGA Acceleration of Multi-Factor CDO Pricing.
ACM Transactions on Reconfigurable Technology and Systems, 4(2):20:1-20:17, May 2011.
paper.pdf (789888)

4

Manuel Saldaña, Arun Patel, Christopher Madill, Daniel Nunes, Danyao Wang, Henry Styles, Andrew Putnam, Ralph Wittig, and Paul Chow.
MPI as a Programming Model for High-Performance Reconfigurable Computers.
ACM Transactions on Reconfigurable Technology and Systems, 3(4):22:1-22:29, November 2010.

5

Daniel Ly and Paul Chow.
A High-Performance, Reconfigurable Hardware Architecture for Restricted Boltzmann Machines.
IEEE Transactions on Neural Networks, 21(11):1780-1792, November 2010.

6

Manuel Saldaña, Emanuel Ramalho, and Paul Chow.
A Message-Passing Hardware/Software Co-simulation Environment for Reconfigurable Computing Systems.
International Journal of Reconfigurable Computing, vol. 2009, 2009.
Article ID 376232, 9 pages, doi:10.1155/2009/376232 Online link

7

William Lo, Keith Redmond, Jason Luu, Paul Chow, Jonathan Rose, and Lothar Lilge.
Hardware acceleration of a Monte Carlo simulation for photodynamic therapy treatment planning.
Journal of Biomedical Optics, 14(1):014019, 2009.
11 pages. Selected for the March 1, 2009 issue of Virtual Journal of Biological Physics Research. Only about 10% of articles are selected.

8

Tor M. Aamodt and Paul Chow.
Compile-Time and Instruction Set Methods for Improving Floating- to Fixed-Point Conversion Accuracy.
ACM Transactions on Embedded Computing Systems, 7(3):1-27, April 2008.
paper.pdf (730869)

9

Manuel Saldaña, Lesley Shannon, Jia Shuo Yue, Sikang Bian, John Craig, and Paul Chow.
Routability of Network Topologies in FPGAs.
IEEE Transactions on Very Large Scale Integration Systems, 15(8):948 - 951, August 2007.
paper.pdf (624301)

10

Lesley Shannon and Paul Chow.
SIMPPL: An Adaptable SoC Framework using a Programmable Controller IP Interface to Facilitate Design Reuse.
IEEE Transactions on Very Large Scale Integration Systems, 15(4):377 - 390, April 2007.
paper.pdf (559017)

11

L. Louis Zhang, Brent Beacham, Massoud Reza Hashemi, Paul Chow, and Alberto Leon-Garcia.
A Scheduler ASIC for a Programmable Packet Switch.
IEEE Micro, 20(1):42-48, January/February 2000.
paper.pdf (357542)

12

Keith I. Farkas, Paul Chow, Norman P. Jouppi, and Zvonko Vranesic.
The Multicluster Architecture: Reducing Cycle Time Through Partitioning.
International Journal of Parallel Programming, 27(5):327-356, October 1999.

13

Paul Chow, Soon Ong Seo, Jonathan Rose, Kevin Chung, Gerard Páez-Monzón, and Immanuel Rahardja.
The Design of an SRAM-Based Field-Programmable Gate Array, Part II: Circuit Design and Layout.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 7(3):321-330, September 1999.
paper.pdf (528590)

14

Paul Chow, Soon Ong Seo, Jonathan Rose, Kevin Chung, Gerard Páez-Monzón, and Immanuel Rahardja.
The Design of an SRAM-Based Field-Programmable Gate Array, Part I: Architecture.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 7(2):191-197, June 1999.
paper.pdf (178930)

15

David M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, and Paul Chow.
The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System.
IEEE Transactions on VLSI Systems, 6(2):188-198, June 1998.
paper.pdf (190473)

16

Gennady Feygin, P. Glenn Gulak, and Paul Chow.
Minimizing Excess Code Length and VLSI Complexity in the Multiplication Free Approximation of Arithmetic Coding.
Journal of Information Processing and Management: Special Issue on Data Compression, 30(6):805-816, 1994.

17

Gennady Feygin, Patrick Glenn Gulak, and Paul Chow.
A Multiprocessor Architecture for Viterbi Decoders with Linear Speed-Up.
IEEE Transactions on Signal Processing, 41(9):2907-2917, September 1993.
paper.pdf (960806)

18

Satwant Singh, Jonathan Rose, Paul Chow, and David Lewis.
The Effect of Logic Block Architecture on FPGA Performance.
IEEE Journal of Solid-State Circuits, 27(3):281-287, March 1992.
paper.pdf (724665)

19

Jonathan Rose, Robert J. Francis, David Lewis, and Paul Chow.
Architecture of Field Programmable Gate Arrays: The Effect of Logic Block Functionality on Area Efficiency.
IEEE Journal of Solid-State Circuits, 25(5):1217-1225, October 1990.
paper.pdf (828316)

20

Mark Horowitz, Paul Chow, Don Stark, Richard Simoni, Arturo Salz, Steven Przybylski, John Hennessy, Glenn Gulak, Anant Agarwal, and John Acken.
MIPS-X: A 20 MIPS Peak, 32-Bit Microprocessor with On-Chip Cache.
IEEE Journal of Solid-State Circuits, SC-22(5):790-799, October 1987.

21

Paul Chow, Z. G. Vranesic, and J. L. Yen.
A Pipelined Distributed Arithmetic PFFT Processor.
IEEE Transactions on Computers, C-32(12):1128-1136, December 1983.

Review Articles

1

Paul Chow.
Reduced Instruction Set Computers.
IEEE Potentials, pages 28-31, October 1991.
paper.pdf (527378)

Refereed Full Papers in Conference Proceedings

1

Charles Lo and Paul Chow.
A High-Performance Architecture for Training Viola-Jones Object Detectors.
In IEEE International Conference on Field-Programmable Technology (FPT), 2012.
8 pages.

2

Vince Mirian and Paul Chow.
Managing Mutex Variables in a Cache-Coherent Shared-Memory System For FPGAs.
In IEEE International Conference on Field-Programmable Technology (FPT), 2012.
4 pages.

3

Yuan Li, Paul Chow, Jiang Jiang, Minxuan Zhang, and Shaojun Wei.
Software/Hardware Framework for Generating Parallel Gaussian Random Numbers Based on the Monty Python Method.
In IEEE International Conference on Field-Programmable Technology (FPT), 2012.

4

Zhongduo Lin, Charles Lo, and Paul Chow.
K-Means Implementation on FPGA for High-Dimensional Data Using Triangle Inequality.
In IEEE International Conference on Field-Programmable Logic and Applications (FPL 2012), page 6 pages, 2012.

5

Vincent Mirian and Paul Chow.
FCache: A System for Cache Coherent Processing on FPGAs.
In International Symposium on Field-Programmable Gate Arrays, pages 233-236. ACM, April 2012.
This is a short paper: 20/87 (25%) full papers accepted and an additional 16 (+18%) short papers accepted.

6

Yuan Li, Paul Chow, Jiang Jiang, and Minxuan Zhang.
Software/Hardware Framework for Generating Parallel Long-Period Random Numbers Using the WELL Method.
In IEEE International Conference on Field-Programmable Logic and Applications (FPL 2011), pages 110-115, August 2011.
57/202 (28%) submissions accepted.

7

Yuanxi Peng, Manuel Saldaña, and Paul Chow.
Hardware Support for Broadcast and Reduce in MPSOC.
In IEEE International Conference on Field-Programmable Logic and Applications (FPL 2011), pages 144-150, August 2011.
57/202 (28%) submissions accepted, Nominated for the Stamatis Vassiliadis Outstanding Paper Award.

8

Charles Lo and Paul Chow.
Building a Multi-FPGA Virtualized Restricted Boltzmann Machine Architecture using Embedded MPI.
In ACM International Symposium on Field-Programmable Gate Arrays (FPGA), pages 189-198, February 2011.
21/82 (26%) submissions accepted.

9

Manuel Saldaña, Arun Patel, Hao Jun Liu, and Paul Chow.
Using Partial Reconfiguration in an Embedded Message-Passing System.
In 2010 International Conference on ReConFigurable Computing and FPGAs (ReConFig'10), pages 418-423, December 2010.

10

H. Bannazadeh, A. Leon-Garcia, K. Redmond, G. Tam, A. Khan, M. Ma, S. Dani, and P. Chow.
Virtualized Application Networking Infrastructure.
In T. Magedanz et al. (Eds.), editor, Tridentcom 2010, LNICST 46, pages 363-382. Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, May 2010.

11

Andrew W.H. House, Manuel Saldaña, and Paul Chow.
Integrating High-Level Synthesis into MPI.
In IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'10), pages 175-178, May 2010.
This is a short paper: 23/132 (17%) full papers accepted and an additional 18 (+14%) short papers accepted.

12

Dharmendra Gupta and Paul Chow.
Acceleration of an Analytical Approach to Collateralized Debt Obligation Pricing.
In International Symposium on Field-Programmable Gate Arrays, pages 103-106. ACM, February 2010.
This is a short paper: 24/96 (25%) full papers accepted and an additional 10 (+10%) short papers accepted.

13

Daniel Le Ly, Manuel Saldaña, and Paul Chow.
The Challenges of Using An Embedded MPI for Hardware-based Processing Nodes.
In IEEE International Conference on Field-Programmable Technology (FPT), pages 120-127, 2009.
32/160 (20%) submissions accepted.

14

Daniel L. Ly and Paul Chow.
A Multi-FPGA Architecture for Stochastic Restricted Boltzmann Machines.
In IEEE International Conference on Field-Programmable Logic and Applications (FPL 2009), pages 168-173, August 2009.
66/247 (27%) submissions accepted.

15

Paul Chow, Manuel Saldaña, Arun Patel, and Chris Madill.
The ArchES Computing Systems Hybrid Computing Platform.
In Hot Chips 21: A Symposium on High Performance Chips. IEEE, August 2009.
20/110 (18%) submissions accepted.

16

Jason Luu, Keith Redmond, William Chun Yip Lo, Paul Chow, Lothar Lilge, and Jonathan Rose.
FPGA-based Monte Carlo Computation of Light Absorption for Photodynamic Cancer Therapy.
In IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'09), April 2009.
8 pages, 25/94 (27%) submissions accepted.

17

Daniel Ly and Paul Chow.
A High-Performance FPGA Architecture for Restricted Boltzmann Machines.
In ACM International Symposium on Field-Programmable Gate Arrays (FPGA), pages 73-82, February 2009.
24/92 (27%) submissions accepted.

18

Daniel Nunes and Paul Chow.
A Profiler for a Heterogeneous Multi-Core Multi-FPGA System.
In IEEE International Conference on Field-Programmable Technology (FPT), pages 113-120, December 2008.
31/135 (23%) submissions accepted.

19

Manuel Saldaña, Emanuel Ramalho, and Paul Chow.
A Message-passing Hardware/Software Co-simulation Environment to Aid in Reconfigurable Computing Design using TMD-MPI.
In 2008 International Conference on ReConFigurable Computing and FPGAs (ReConFig'08), pages 265-270, December 2008.
76/125 (61%) full submissions accepted. paper.pdf (180823)

20

Alexander Kaganov, Asif Lakhany, and Paul Chow.
FPGA Acceleration of Monte-Carlo Based Credit Derivative Pricing.
In IEEE International Conference on Field-Programmable Logic and Applications (FPL 2008), pages 329-334, September 2008.
69/247 (28%) submissions accepted. paper.pdf (280427), slides.pdf (437231)

21

Samir Parikh, Glenn Gulak, and Paul Chow.
A CMOS Image Sensor for DNA Microarrays.
In IEEE Custom Integrated Circuits Conference, pages 821-824, September 2007.
paper.pdf (627350)

22

Sam Lee and Paul Chow.
An FPGA Implementation of Reciprocal Sums for SPME.
In 2007 International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'07), pages 159-165, June 2007.
paper.pdf (152253), slides.pdf (486003)

23

Tor Aamodt and Paul Chow.
Optimization of Data Prefetch Helper Threads with Path-Expression Based Statistical Modeling.
In 21st ACM International Conference on Supercomputing, pages 210-221, June 2007.
paper.pdf (365112)

24

Chichyang Chen and Paul Chow.
Design of a Versatile and Cost-Effective Hybrid Floating-Point/LNS Arithmetic Processor.
In GLSVLSI '07: Proceedings of the 17th Great Lakes Symposium on VLSI, pages 540-545. ACM, March 2007.
paper.pdf (90932)

25

Manuel Saldaña, Daniel Nunes, Emanuel Ramalho, and Paul Chow.
Configuration and Programming of Heterogeneous Multiprocessors on a Multi-FPGA System Using TMD-MPI.
In 3rd International Conference on ReConFigurable Computing and FPGAs 2006 (ReConFig'06), September 2006.
8 pages. paper.pdf (666063)

26

Lesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, and Paul Chow.
A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification.
In IEEE International Conference on Field-Programmable Logic and Applications (FPL 2006), pages 289-294, August 2006.
85/307 (28%) full submissions accepted. paper.pdf (92869)

27

Manuel Saldaña and Paul Chow.
TMD-MPI: An MPI Implementation for Multiple Processors across Multiple FPGAs.
In IEEE International Conference on Field-Programmable Logic and Applications (FPL 2006), pages 329-334, August 2006.
85/307 (28%) full submissions accepted. paper.pdf (155296)

28

Arun Patel, Christopher Madill, Manuel Saldaña, Christopher Comis, Régis Pomès, and Paul Chow.
A Scalable FPGA-based Multiprocessor.
In IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'06), pages 111-120, April 2006.
25/123 (20%) submissions accepted. paper.pdf (270858)

29

Manuel Saldaña, Lesley Shannon, and Paul Chow.
The Routability of Multiprocessor Network Topologies in FPGAs.
In SLIP'06: International Workshop on System-Level Interconnect, pages 49-56. ACM/IEEE, March 2006.
paper.pdf (358305)

30

Lesley Shannon and Paul Chow.
Simplifying the Integration of Processing Elements in Computing Systems using a Programmable Controller.
In IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05), pages 63-72, April 2005.
25/90 (28%) submissions accepted. paper.pdf (162539)

31

Lesley Shannon and Paul Chow.
Maximizing System Performance: Using Reconfigurability to Monitor System Communications.
In International Conference on Field-Programmable Technology (FPT), pages 231-238, Brisbane, Australia, December 2004.
34/122 (28%) submissions accepted. paper.pdf (169860)

32

Navid Azizi, Ian Kuon, Aaron Egier, Ahmad Darabiha, and Paul Chow.
Reconfigurable Molecular Dynamics Simulator.
In Symposium on Field-Programmable Custom Computing Machines (FCCM'04), pages 197-206. IEEE, April 2004.
25/91 (27%) submissions accepted. paper.pdf (173430), slides.pdf (356937), slidesdetailed.pdf (526704)

33

Lesley Shannon and Paul Chow.
Using Reconfigurability to Achieve Real-Time Profiling for Hardware/Software Codesign.
In International Symposium on Field-Programmable Gate Arrays, pages 190-199. ACM, February 2004.
24/90 (27%) submissions accepted. paper.pdf (146510), poster.pdf (99013)

34

Tor M. Aamodt, Paul Chow, Per Hammarlund, Hong Wang, and John Shen.
Hardware Support for Prescient Instruction Prefetch.
In $10^{\mbox{th}}$ International Symposium on High-Performance Computer Architecture, pages 84-95. IEEE, February 2004.
27/153 (18%) submissions accepted. paper.pdf (479428)

35

Tor Aamodt, Pedro Marcuello, Paul Chow, Antonio Gonzalez, Per Hammarlund, Hong Wang, and John P. Shen.
A Framework for Modeling and Optimization of Prescient Instruction Prefetch.
In SIGMETRICS '03, pages 13-24. ACM, June 2003.
Acceptance rate 12%. paper.pdf (444790)

36

Jorge E. Carrillo E. and Paul Chow.
The Effect of Reconfigurable Units in Superscalar Processors.
In International Symposium on Field-Programmable Gate Arrays, pages 141-150. ACM, February 2001.
paper.ps (363276), paper.ps.gz (146728), paper.pdf (201396)

37

Tor Aamodt and Paul Chow.
Embedded ISA Support for Enhanced Floating-Point to Fixed-Point ANSI C Compilation.
In International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES 2000), pages 128-137, November 2000.
paper.ps (998950), paper.ps.gz (155690), paper.pdf (396784), slides.ppt (1120768)

38

L. Louis Zhang, Brent Beacham, Massoud Hashemi, Paul Chow, and Alberto Leon-Garcia.
Design and Implementation of a Scheduler Engine for a Programmable Packet Switch.
In IEEE Hot Interconnects 7, 1999.
Presented August 18, 1999.

39

Ivan Hamer and Paul Chow.
DES Cracking on the Transmogrifier 2a.
In Cetin Kaya Koc and Christof Paar, editors, Cryptographic Hardware and Embedded Systems, pages 13-24. Springer-Verlag Lecture Notes in Computer Science (LNCS 1717), 1999.
Presented August 12, 1999. paper.ps (693539), paper.ps.gz (80614), slides

40

Jeffrey A. Jacob and Paul Chow.
Memory Interfacing and Instruction Specification for Reconfigurable Processors.
In International Symposium on Field-Programmable Gate Arrays, pages 145-154. ACM/SIGDA, February 1999.
paper.ps (811055), paper.ps.gz (236224), paper.pdf (95228)

41

Keith Farkas, Paul Chow, Norman Jouppi, and Zvonko Vranesic.
The Multicluster Architecture: Reducing Cycle Time Through Partitioning.
In The 30th Annual International Symposium on Microarchitecture: MICRO-30, pages 149-159, Research Triangle Park, NC, December 1997. IEEE Computer Society/ACM.
paper.ps (250303), paper.ps.gz (60557), paper.pdf (92066)

42

Keith I. Farkas, Paul Chow, Norman P. Jouppi, and Zvonko Vranesic.
Memory-System Design Considerations for Dynamically-Scheduled Processors.
In The 24th Annual International Symposium on Computer Architecture, pages 133-143. IEEE/ACM, June 1997.
An extended version is available as WRL Research Report 97/1. paper.ps (684713), paper.ps.gz (98279), paper.pdf (160092), Report 97/1

43

David M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, and Paul Chow.
The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System.
In 1997 International Symposium on Field-Programmable Gate Arrays, pages 53-61. ACM/SIGDA, February 1997.
paper.ps.gz (409501)

44

Mazen A.R. Saghir, Paul Chow, and Corinna G. Lee.
Exploiting Dual Memory Banks in Digital Signal Processors.
In 1996 SIGARCH Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS VII), pages 234-243, Boston, MA, October 1996.
paper.ps.gz (54915)

45

Ralph D. Wittig and Paul Chow.
OneChip: An FPGA Processor With Reconfigurable Logic.
In The Fourth Annual IEEE Symposium on FPGAs for Custom Computing Machines FCCM'96, pages 126-135. IEEE, March 1996.
paper.ps (155887), paper.ps.gz (49472), paper.pdf (1059698), slides.ps.gz (29628)

46

David Yeh, Gennady Feygin, and Paul Chow.
RACER: A Reconfigurable Constraint-Length 14 Viterbi Decoder.
In The Fourth Annual IEEE Symposium on FPGAs for Custom Computing Machines FCCM'96, pages 60-69. IEEE, March 1996.
paper.ps (190678), paper.ps.gz (58685), paper.pdf (1059698), slides.ps.gz (196452)

47

Keith I. Farkas, Norman P. Jouppi, and Paul Chow.
Register File Design Configurations in Dynamically Scheduled Processors.
In The 2nd International Symposium on High-Performance Computer Architecture, pages 40-51. IEEE, February 1996.
Also available as WRL Research Report 95/10. paper.ps (449232), paper.ps.gz (86453), paper.pdf (125672), Report 95/10

48

Paul Chow, David Karchmer, Paul Chow, Ron White, Tony Ngai, Paul Hodgins, David Yeh, Jeewika Ranaweera, Indra Widjaja, and Al Leon-Garcia.
A 50,000 Transistor Packet-Switching Chip for the StarBurst ATM Switch.
In Custom Integrated Circuits Conference, pages 435-438. IEEE, May 1995.
This paper was cited in EE Times, May 8, 1995. paper.pdf (387180)

49

Paul Chow, Paul Chow, and P. Glenn Gulak.
A Field-Programmable Mixed-Analog-Digital Array.
In 1995 International Symposium on Field-Programmable Arrays, pages 104-109. ACM/SIGDA, February 1995.
paper.pdf (113781)

50

Keith I. Farkas, Norman P. Jouppi, and Paul Chow.
How Useful are Non-blocking Loads, Stream Buffers, and Speculative Execution in Multiple Issue Processors?
In First International Symposium on High-Performance Computer Architecture, pages 78-89. IEEE/ACM, January 1995.
Also available as WRL Research Report 94/8. paper.pdf (850409), Report 94/8

51

Gennady Feygin, P. Glenn Gulak, and Paul Chow.
Architectural Advances in the VLSI Implementation of Arithmetic Coding for Binary Image Compression.
In Data Compression Conference DCC '94, pages 254-263. IEEE, March 1994.
paper.pdf (443679)

52

Mazen A.R. Saghir, Paul Chow, and Corinna G. Lee.
Application-Driven Design of DSP Architectures and Compilers.
In 1994 International Conference on Acoustics, Speech, and Signal Processing, pages II-437-II-440, Adelaide, Australia, April 1994. IEEE.
paper.pdf (347876)

53

Gennady Feygin, Paul Chow, P. Glenn Gulak, John Chappel, Grant Goodes, Oswin Hall, Ahmad Sayes, Satwant Singh, Michael B. Smith, and Steve Wilton.
A VLSI Implementation of a Cascade Viterbi Decoder with Traceback.
In 1993 IEEE International Symposium on Circuits and Systems, pages 1945-1948, May 1993.
paper.pdf (355733)

54

Paul Chow, Soon Ong Seo, Kevin Chung, Gerard Paez, and Jonathan Rose.
A High-Speed FPGA Using Programmable Mini-tiles.
In Symposium on Integrated Systems, previously the Conference on Advanced Research in VLSI, pages 103-122, March 1993.
paper.ps (664109), paper.ps.gz (101397)

55

Gennady Feygin, P. Glenn Gulak, and Paul Chow.
Minimizing Error and VLSI Complexity in the Multiplication Free Approximation of Arithmetic Coding.
In Data Compression Conference DCC '93, pages 118-127. IEEE, March 1993.
paper.pdf (387990)

56

Qing Zheng and Paul Chow.
EXsim: A General Purpose Object-Oriented Environment for Discrete-Event Simulations.
In Object-Oriented Simulation Conference (OOS '93) of the 1993 Western Simulation MultiConference, pages 15-21, San Diego, January 1993.

57

Satwant Singh, Jonathan Rose, David Lewis, Kevin Chung, and Paul Chow.
Optimization of Field-Programmable Gate Array Logic Block Architecture for Speed.
In Custom Integrated Circuits Conference, pages 6.1.1-6.1.6. IEEE, May 1991.
paper.pdf (409783)

58

Michael Takefman and Paul Chow.
A Streamlined DSP Microprocessor Architecture.
In International Conference on Acoustics, Speech, and Signal Processing, pages 1257-1260, Toronto, May 1991. IEEE.
paper.pdf (571448)

59

Gennady Feygin, Patrick Glenn Gulak, and Paul Chow.
Generalized Cascade Viterbi Decoder--A Locally Connected Multiprocessor with Linear Speed-Up.
In International Conference on Acoustics, Speech, and Signal Processing, pages 1097-1100, Toronto, May 1991.
paper.pdf (612785)

60

Grant Goodes and Paul Chow.
A Methodology for Large Chip Design in the Cadence Edge Environment.
In CCVLSI'90, pages 6.8.1-6.8.8, Ottawa, October 1990.

61

Paul Chow, David Lewis, Vijaya Singh, Gabriel Varga, and Steve Wood.
AWSIM 1.5: A Microprocessor for Circuit Simulation.
In CCVLSI'90, pages 3.4.1-3.4.8, Ottawa, October 1990.

62

Jonathan Rose, Robert J. Francis, Paul Chow, and David Lewis.
The Effect of Logic Block Complexity on Area of Programmable Gate Arrays.
In Custom Integrated Circuits Conference, pages 5.3.1-5.3.5. IEEE, May 1989.
paper.pdf (331773)

63

Paul Chow and Mark Horowitz.
The Design and Testing of MIPS-X.
In Fifth MIT Conference on Advanced Research in VLSI, pages 95-114, MIT, Cambridge, MA, March 1988.

64

Paul Chow and Mark Horowitz.
Architectural Tradeoffs in the Design of MIPS-X.
In The 14th Annual International Symposium on Computer Architecture, pages 300-308, Pittsburg, Pennsylvania, June 1987. IEEE.
This article also appears in William Stallings, Reduced Instruction Set Computers, 2nd Edition, IEEE Computer Society Press Tutorial, 1990, pp. 230-238.

65

Anant Agarwal, Paul Chow, Mark Horowitz, John Acken, Arturo Salz, and John Hennessy.
On-Chip Instruction Caches for High-Performance Processors.
In 1987 Stanford Conference on Advanced Research in VLSI, pages 1-24, Stanford, California, March 1987.

66

Mark Horowitz, John Hennessy, Paul Chow, Glenn Gulak, John Acken, Anant Agarwal, Chorng-Yeung Chu, Scott McFarling, Steven Przybylski, Steve Richardson, Arturo Salz, Richard Simoni, Don Stark, Peter Steenkiste, Steve Tjiang, and Malcolm Wing.
A 32b Microprocessor with On-Chip 2Kbyte Instruction Cache.
In ISSCC Digest of Technical Papers, pages 30-31, 328, February 1987.

67

Paul Chow, Z. G. Vranesic, and J. L. Yen.
A Pipelined Distributed Arithmetic Processor.
In Proceedings of the Fifth Symposium on Computer Arithmetic, pages 198-206, May 1981.

68

Paul Chow, Z. G. Vranesic, and J. L. Yen.
Microprocessor Implementations of Discrete Fourier Transform Machines.
In Compcon Fall, pages 316-320. IEEE, 1979.
paper.pdf (358912)

Full Papers from Refereed Abstracts

1

Mazen A.R. Saghir, Paul Chow, and Corinna G. Lee.
Automatic Data Partitioning for HLL DSP Compilers.
In The Sixth International Conference on Signal Processing Applications and Technology, ICSPAT'95, pages 866-871, Boston, MA, October 1995.
paper.ps.gz (28838)

2

Sanjay Pujare, Corinna G. Lee, and Paul Chow.
Machine-Independent Compiler Optimizations for the UofT DSP Architecture.
In The Sixth International Conference on Signal Processing Applications and Technology, ICSPAT'95, pages 860-865, Boston, MA, October 1995.
paper.ps.gz (30726)

3

Wen-Yen Lin, Corinna G. Lee, and Paul Chow.
An Optimizing Compiler for the TMS320C25 DSP Chip.
In The Fifth International Conference on Signal Processing Applications and Technology, ICSPAT'94, pages 689-694, Dallas, Texas, October 1994.
paper.ps.gz (29185),

4

Mazen A.R. Saghir, Paul Chow, and Corinna G. Lee.
Towards Better DSP Architectures and Compilers.
In The Fifth International Conference on Signal Processing Applications and Technology, ICSPAT'94, pages 658-664, Dallas, Texas, October 1994.
paper.ps.gz (35626),

5

David Yeh, Paul Chow, and Gennady Feygin.
A Multiprocessor Viterbi Decoder Using Xilinx FPGAs.
In 1994 Canadian Workshop on Field-Programmable Devices, Kingston, Ontario, June 1994.
paper.ps.gz (44485)

6

David Galloway, David Karchmer, Paul Chow, David Lewis, and Jonathan Rose.
The Transmogrifier: The University of Toronto Field-Programmable System.
In 1994 Canadian Workshop on Field-Programmable Devices, Kingston, Ontario, June 1994.
paper.ps.gz (20279)

7

Paul Chow, Soon Ong Seo, Dennis Au, Terrence Choy, Bahram Fallah, David Lewis, Cherry Li, and Jonathan Rose.
A 1.2$\mu$m CMOS FPGA Using Cascaded Logic Blocks and Segmented Routing.
In Will Moore and Wayne Luk, editors, FPGAs, chapter 3.2, pages 91-102. Abingdon EE&CS Books, 15 Harcourt Way, Abingdon OX14 1NV, England, 1991.
Presented at the Oxford 1991 International Workshop on Field Programmable Logic and Applications, paper.ps.gz (60692), paper.pdf (51599)

8

Kevin Chung, Satwant Singh, Jonathan Rose, and Paul Chow.
Using Hierarchical Logic Blocks to Improve the Speed of Field-Programmable Gate Arrays.
In Will Moore and Wayne Luk, editors, FPGAs, chapter 3.3, pages 103-113. Abingdon EE&CS Books, 15 Harcourt Way, Abingdon OX14 1NV, England, 1991.
Presented at the Oxford 1991 International Workshop on Field Programmable Logic and Applications.

Workshop Papers and Presentations

1

Paul Chow.
Bringing High-Performance Reconfigurable Computing into the Mainstream.
2010 CMOS Emerging Technologies Workshop, May 2010.
Whistler, BC, Canada, Invited talk.

2

Paul Chow.
A Programming Model for High-Performance Reconfigurable Computing.
Workshop on Algorithmic Re-engineering for Modern Non-Conventional Processing Units, October 2009.
Lugano, Switzerland, Invited talk.

3

Keith Redmond, Hadi Bannazadeh, Paul Chow, and Alberto Leon-Garcia.
Development of a Virtual Application Networking Infrastructure Node.
In 3rd IEEE Workshop on Enabling the Future Service-Oriented Internet - Towards Socially-Aware Networks (EFSOI 09), December 2009.

4

Manuel Saldaña, Arun Patel, Christopher Madill, Daniel Nunes, Danyao Wang, Henry Styles, Andrew Putnam, Ralph Wittig, and Paul Chow.
MPI as an Abstraction for Software-Hardware Interaction for HPRCs.
In Second International Workshop on High-Performance Reconfigurable Computing Technology and Applications, 2008.
10 pages. Held in conjunction with Supercomputing 2008. Received the OpenFPGA Award for Advancement in Industry Standards in Reconfigurable Computing. paper.pdf (405927)

5

Andrew W.H. House and Paul Chow.
Toward a Programming Model for Emerging High-Performance Computing Architectures.
WoSPS: Workshop on Soft Processor Systems, In conjunction with The Seventeenth International Conference on Parallel Architectures and Compilation Techniques (PACT), October 2008.
5 pages, paper.pdf (814395), slides.pdf (623635)

6

Arun Patel, Manuel Saldaña, Chris Madill, and Paul Chow.
An MPI Approach to High-Performance Computing with FPGAs.
SHARCNET Symposium on GPU and Cell Computing, May 2008.
University of Waterloo.

7

Paul Chow.
Biomolecular Simulations on an FPGA Cluster.
2007 CMOS Emerging Technologies Workshop, July 2007.
Whistler, BC, Canada, Invited talk.

8

Tor Aamodt, Pedro Marcuello, Paul Chow, Per Hammarlund, and Hong Wang.
Prescient Instruction Prefetch.
In MTEAC-6 (in conjunction with MICRO-35), pages 3-10, 2002.
Won best student paper award. paper.pdf (127721)

9

Tor Aamodt, Andreas Moshovos, and Paul Chow.
The Predictability of Computations that Produce Unpredictable Outcomes.
In MTEAC-5 (in conjunction with MICRO-34), pages 23-34, 2001.
paper.pdf (192626)

10

Marcus van Ierssel, David Galloway, Paul Chow, and Jonathan Rose.
The Transmogrifier-3a: Hardware and Software for a 3 Million Gate Rapid Prototyping System.
In Micronet Annual Workshop, April 2001.
This paper won the best paper award in the Systems Area.

11

Tor Aamodt and Paul Chow.
Numerical Error Minimizing Floating-Point to Fixed-Point ANSI C Compilation.
In 1st Workshop on Media Processors and DSPs (MPDSP-1 in conjunction with MICRO-32), pages 3-12, 1999.
paper.ps.gz (111792), paper.pdf (290065)

12

Mazen A. R. Saghir, Paul Chow, and Corinna G. Lee.
A Comparison of Traditional and VLIW DSP Architectures for Compiled DSP Applications.
In International Workshop on Compiler and Architecture Support for Embedded Computing Systems-CASES'98, December 1998.
5 pages. paper.ps.gz (26100), slides.ps.gz (34271)

Poster Presentations

1

Stephen Alexander Chin and Paul Chow.
Reusable OpenCL FPGA Infrastructure.
In International Symposium on Field-Programmable Gate Arrays Poster Session. ACM, February 2012.

2

Charles Lo and Paul Chow.
Building a Multi-FPGA Virtualized Restricted Boltzmann Machine Architecture Using Embedded MPI.
The CMC Microsystems 2010 Annual Symposium TEXPO Demonstration, October 2010.

3

Daniel Ly and Paul Chow.
A Novel FPGA Framework for Restricted Boltzmann Machines.
The CMC Microsystems 2008 Annual Symposium TEXPO Demonstration, October 2008.

4

Dharmendra Gupta, David Woods, and Paul Chow.
Parallel 2-D Wave Equation Simulation using MPI Berkeley Emulation Engine 2 (BEE2).
The CMC Microsystems 2008 Annual Symposium TEXPO Demonstration, October 2008.

5

Alexander Kaganov, Asif Lakhany, Paul Chow, and Alex Kreinin.
FPGA Acceleration of Monte-Carlo Based Credit Derivatives Pricing.
Eighth International Conference on Monte Carlo and Quasi-Monte Carlo Methods in Scientific Computing Poster Presentation, July 2008.

6

Andrew House and Paul Chow.
Investigation of Programming Models for Emerging FPGA-Based High Performance Computing Systems.
IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '08) Poster Session, April 2008.

7

Alex Kaganov, Daniel Nunes, Emanuel Ramalho, Arun Patel, Chris Madill, Manuel Saldaña, Régis Pomès, and Paul Chow.
High-Performance Computing with Multi-FPGA Systems.
Microsystems Research and Development in Canada 2007 (MR&DCAN) TEXPO Poster, October 2007.
poster.pdf (11928037)

8

Manuel Saldaña, Daniel Nunes, Emanuel Ramalho, and Paul Chow.
Configuration and Programming of Heterogeneous Multiprocessors on a Multi-FPGA System Using TMD-MPI.
Microsystems Research and Development in Canada 2006 (MR&DCAN) TEXPO Poster, October 2006.
poster.pdf (13513807)

9

Manuel Saldaña, Lesley Shannon, and Paul Chow.
The Routability of Multiprocessor Network Topologies in FPGAs.
ACM International Symposium on Field-Programmable Gate Arrays poster, February 2006.
poster.pdf (4251046)

10

Lesley Shannon, Blair Fort, Arun Patel, Samir Parikh, Manuel Saldaña, and Paul Chow.
Designing an FPGA SoC using a Standardized IP Block Interface.
IEEE International Conference on Field-Programmable Technology (FPT) poster, December 2005.
poster.pdf (68291)

11

Arun Patel, Christopher Madill, Manuel Saldaña, Christopher Comis, Dave Chui, Sam Lee, Régis Pomès, and Paul Chow.
Accelerating Biomolecular Simulation using a Scalable Network of Reconfigurable Hardware.
CMC Microsystems 2005 Annual Symposium TEXPO Poster, October 2005.
poster.pdf (6954902)

12

Lesley Shannon and Paul Chow.
Leveraging Reconfigurability in the Design Process.
IEEE International Conference on Field-Programmable Logic and Applications (FPL) PhD Forum poster, August 2005.
poster.pdf (59538)

13

Lesley Shannon and Paul Chow.
Leveraging Reconfigurability in the Design Process.
Microsystems Research and Development in Canada 2004 (MR&DCAN) TEXPO Poster, September 2004.
Winner of the CMC Componentware/CAD Award poster.pdf (138977)

14

Ian Kuon, Navid Azizi, Ahmad Darabiha, Aaron Egier, and Paul Chow.
FPGA-Based Supercomputing: An Implementation for Molecular Dynamics.
ACM International Symposium on Field-Programmable Gate Arrays Poster Session, February 2004.
poster.pdf (3663118)

15

Lesley Shannon and Paul Chow.
Standardizing the Performance Assessment of Reconfigurable Processor Architectures.
IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '03) Poster Session, April 2003.

16

Sean Peng and Paul Chow.
A VLIW Programmable DSP Processor in TSMC 0.35 $\mu m$ CMOS.
Microsystems Research and Development in Canada (MR&DCAN'99) TEXPO Poster, June 1999.
Winner of the CMC International Travel Award.

17

Louis Zhang, Brent Beacham, and Paul Chow.
A Single-Queue Multicast Packet/Cell Scheduler ASIC for Packet/Cell Switching.
Microsystems Research and Development in Canada (MR&DCAN'98) TEXPO Poster, June 1998.
Winner of the Canadian Semiconductor Design Association Award.

18

Marcus van Ierssel and Paul Chow.
The Transmogrifier-2 Field Programmable System.
Microsystems Research and Development in Canada (MR&DCAN'97) TEXPO Poster, 1997.
Winner of the CMC International Travel Award.

Books and Book Chapters

1

Paul Chow, editor.
The MIPS-X RISC Microprocessor.
Kluwer Academic Publishers, 1989.
ISBN 0-7923-9045-8.

2

Paul Chow and John Hennessy.
Reduced Instruction Set Computer Architectures.
In Veljko M. Milutinovic, editor, Computer Architecture: Concepts and Systems, chapter 2, pages 48-83. Elsevier Science Publishing Co. (North Holland), New York, 1988.
ISBN 0-444-01019-X.

Invited Whitepaper

1

Paul Chow and Dan Gale.
The New Technology Challenge: CMC's Changing Roles.
Published by Canadian Microelectronics Corporation, March 2004.
This paper provided the vision upon which CMC built its 2004 Strategic Plan and, subsequently, its successful proposal to NSERC for renewal in the 2005-2010 period. paper.pdf (746903)

Invited, Non-refereed Conference Paper

1

Mark Horowitz and Paul Chow.
The MIPS-X Microprocessor.
In Wescon/85, Professional Program Session Record 6, pages 1-6, San Francisco, CA, November 1985. IEEE.

Technical Reports

1

Taneem Ahmed and Paul Chow.
Adding Custom Peripheral to Embedded FPGA Design Running PetaLinux.
Technical Report Application Note 2011-01, CMC Microsystems, 2011.
SKU CMC-00200-01605.

2

Chu Pang, Geng Liu, and Paul Chow.
Extracting PCOREs from BEECube Platform Studio.
Technical Report Application Note 2009-32, CMC Microsystems, 2010.
SKU CMC-00131-54300.

3

Dharmendra Gupta, David Woods, and Paul Chow.
Parallel 2-D Wave Simulation using MPI on Berkeley Emulation Engine 2 (BEE2).
Technical Report Application Note MS-37, CMC Microsystems, March 2009.
SKU CMC-00025-20057.

4

Paul Chow and Robert Jeschke.
CMC Workshop on Using the CMC/University of Toronto Rapid Protyping Board for Teaching and Research: Overheads.
Technical Report IC 95-09, Canadian Microelectronics Corporation, Carruthers Hall, Queen's University, Kingston, ON Canada K7L 3N6, October 1995.
48 pages.

5

Paul Chow and Robert Jeschke.
CMC Workshop on Using the CMC/University of Toronto Rapid Protyping Board for Teaching and Research: Laboratory Exercises.
Technical Report IC 95-10, Canadian Microelectronics Corporation, Carruthers Hall, Queen's University, Kingston, ON Canada K7L 3N6, October 1995.
33 pages.

6

Paul Chow and Robert Jeschke.
CMC/University of Toronto Rapid-Prototyping Board Design Flow Overview/Tools Document.
Technical Report ICI-067, Canadian Microelectronics Corporation, Carruthers Hall, Queen's University, Kingston, ON Canada K7L 3N6, November 1995.
64 pages.

7

Paul Chow and Robert Jeschke.
CMC/University of Toronto Rapid-Prototyping Board User's Guide.
Technical Report ICI-068, Canadian Microelectronics Corporation, Carruthers Hall, Queen's University, Kingston, ON Canada K7L 3N6, November 1995.
91 pages.

8

Arturo Salz, Anant Agarwal, and Paul Chow.
MIPS-X: The External Interface.
Technical Report CSL-TR-87-339, Stanford University, Computer Systems Laboratory, November 1987.
34 pages. An updated version appears as Chapter 7 in The MIPS-X RISC Microprocessor, edited by Paul Chow, Kluwer Academic Publishers, 1989.

9

Paul Chow.
MIPS-X Instruction Set and Programmer's Manual.
Technical Report CSL-86-289, Computer Systems Laboratory, Stanford University, May 1986.
91 pages, paper.pdf (1609728) .

Miscellaneous

1

The Transmogrifier-3 Home Page.
www.eecg.toronto.edu/~tm3.

2

The Transmogrifier-4 Home Page.
www.eecg.toronto.edu/~tm4.

Theses Completed

1

S. Alexander Chin.
Reusable OpenCL FPGA Infrastructure.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, January 2012.
thesis.pdf

2

Taneem Ahmed.
OpenCL Framework for a CPU, GPU, and FPGA Platform.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, September 2011.
thesis.pdf

3

Chris Madill.
A Heterogeneous, Purpose Built Computer Architecture for Accelerating Biomolecular Simulation.
PhD thesis, University of Toronto, Department of Biochemistry, 2011.
thesis.pdf

4

Vincent Mirian.
An Interconnectioin Network for a Cache Coherent System on FPGAs.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, September 2010.
thesis.pdf

5

David Woods.
Coherent Shared Memories for FPGAs.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, September 2009.
thesis.pdf

6

Dharmendra Gupta.
Accelerating an Analytical Approach to Collateralized Debt Obligation Pricing.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, September 2009.
thesis.pdf

7

Keith Thomas Redmond.
Development of a Virtual Applications Networking Infrastructure Node.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, September 2009.
thesis.pdf

8

Daniel Le Ly.
A High-Performance Reconfigurable Architecture for Restricted Boltzmann Machines.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, August 2009.
thesis.pdf

9

Emanuel Ramalho.
The LINPACK Benchmark on a Multi-Core Multi-FPGA System.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, October 2008.
thesis.pdf (878562), slides.ppt (5485568)

10

Daniel Pereira Nunes.
A Profiler for a Heterogeneous Multi-Core Multi-FPGA System.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, September 2008.
thesis.pdf (1764921), slides.ppt (14387200)

11

Alexander Kaganov.
Hardware Acceleration of Monte-Carlo Structural Financial Instrument Pricing Using a Gaussian Copula Model.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, September 2008.
thesis.pdf (968911), slides.ppt (1785344)

12

Samir Parikh.
A CMOS Imager for DNA Detection.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, January 2007.
thesis.pdf (3583350), slides.ppt (7882240)

13

Arun Patel.
A 3D Convolution Engine for Computing the Reciprocal Space Ewald Electrostatic Energy in Molecular Dynamics Simulations.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, January 2007.

14

Manuel Saldaña.
A Parallel Programming Model for a Multi-FPGA Multiprocessor Machine.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, September 2006.

15

Lesley Shannon.
Simplifying System-on-Chip Design through Architecture and System CAD Tools.
PhD thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, August 2006.

16

Tor M. Aamodt.
Modeling and Optimization of Speculative Threads.
PhD thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, October 2005.

17

Christopher Comis.
A High-Speed Inter-Process Communication Architecture for FPGA-based Hardware Acceleration of Molecular Dynamics.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, September 2005.
thesis.pdf (731876), slides.ppt (3116032)

18

Sam Lee.
An FPGA Implementation of the Smooth Particle Mesh Ewald Reciprocal Sum Compute Engine.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, September 2005.
thesis.pdf (1854548), slides.ppt (796160)

19

David Chui.
An FPGA Implementation of the Ewald Direct Space and Lennard-Jones Compute Engines.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, September 2005.
thesis.pdf (1590128), slides.ppt (246272)

20

Amy Wang.
Code Compaction for VLIW Instructions.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, September 2001.
thesis.ps.gz (350203)

21

Tor Michael Aamodt.
Floating-Point to Fixed-Point Compilation and Embedded Architectural Support.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, January 2001.
thesis.ps.gz (642087)

22

Jianghong Hu.
A Datapath Compiler with Technology Portability.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 2000.
thesis.ps.gz (854001), thesis.ps (7171262), thesis.pdf (2771258)

23

Jorge Ernesto Carrillo Esparza.
Evaluation of the OneChip reconfigurable Processor.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, September 2000.
thesis.ps.gz (143442)

24

Lesley Lorraine Shannon.
Impact of Intellectual Property Cores on Field Programmable Gate Array Designs.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, December 2000.
thesis.ps.gz (371401), thesis.ps (2244154), thesis.pdf (939987)

25

Juan Humberto Rico.
HDL-Level Partitioning of Circuits.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, December 2000.
thesis.ps.gz (599100)

26

Scott Nunweiler.
A Case Study in Design for Reuse Using VHDL.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1999.
thesis.ps.gz (628587)

27

Sean Peng.
UTDSP: A VLIW Programmable DSP Processor.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1999.
thesis.ps.gz (3706773), thesis.ps (5391879), thesis.pdf (8900402)

28

Mazen A.R. Saghir.
Application-Specific Instruction-Set Architectures for Embedded DSP Applications.
PhD thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1998.
thesis.ps.gz (362850)

29

Jeffery A. Jacob.
Memory Interfacing for the OneChip Reconfigurable Processor.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1998.
thesis.ps.gz (645782)

30

Vineet Chandra Joshi.
Using the Transmogrifier-2 to Prototype an ATM Wrap Sequencer.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1998.

31

Keith Istvan Farkas.
Memory-system Design Considerations for Dynamically-Scheduled Microprocessors.
PhD thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1997.
thesis.ps (3086589), thesis.ps.gz (551790)

32

Dean D'Mello.
Synthesis of FPAA Cores Using an Intermediate Language Layout Language Approach.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1996.

33

Gennady Feygin.
Arithmetic Coding: Algorithms and VLSI Architectures.
PhD thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1995.
Co-supervised with Glenn Gulak.

34

David Chun-Chin Yeh.
A Multiprocessor Viterbi Decoder Using Xilinx FPGAs.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1995.
thesis.ps.gz (196452)

35

Ralph D. Wittig.
OneChip: An FPGA Processor With Reconfigurable Logic.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1995.
thesis.ps (509116), thesis.ps.gz (151124)

36

Mohamed El Ebiary.
History Guided Prefetching in a Telephone Switching Application.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1994.

37

Paul Chow.
A Field-Programmable Mixed-Analog-Digital Array.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1994.
Co-supervised with Glenn Gulak, thesis.ps.gz (204218)

38

Robert Jeschke.
An FPGA Based Reconfigurable Coprocessor for the IBM PC.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1994.

39

Soong Ong Seo.
A High Speed Field-Programmable Gate Array Using Programmable Minitiles.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1994.
Co-supervised with Jonathan Rose.

40

Harpreet Singh Gill.
Improved Optimization Strategies for Blocked Algorithms.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1994.

41

Pok Yan Lee.
An FPGA Implementation of the DLX.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1993.

42

Sushant Verman.
An FPGA-Based Reconfigurable Computing Array.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1993.

43

Mazen Saghir.
Architectural and Compiler Support for DSP Applications.
Master's thesis, University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1993.

44

Vijaya Singh.
An Optimizing C Compiler for a General Purpose DSP Architecture.
Master's thesis, University of Toronto, Department of Electrical Engineering, Toronto, Ontario, M5S 3G4, 1992.

45

Qing Zheng.
SEP: A General Purpose Object-Oriented Environment for Discrete-Event Simulations.
Master's thesis, University of Toronto, Department of Electrical Engineering, Toronto, Ontario, M5S 3G4, 1992.

46

Grant S. Goodes.
Stache: A Novel Cache Architecture Using Predictive Prefetch.
Master's thesis, University of Toronto, Department of Electrical Engineering, Toronto, Ontario, M5S 3G4, 1991.

47

Satwant Singh.
The Effect of Logic Block Architecture on the Speed of Field-Programmable Gate Arrays.
Master's thesis, University of Toronto, Department of Electrical Engineering, Toronto, Ontario, M5S 3G4, 1991.
Co-supervised with Jonathan Rose.

48

Michael Takefman.
Improving the Performance of a DSP Microprocessor Architecture.
Master's thesis, University of Toronto, Department of Electrical Engineering, Toronto, Ontario, M5S 3G4, 1990.

49

Gennady Feygin.
A Multiprocessor Architecture for Viterbi Decoders with Linear Speed-up.
Master's thesis, University of Toronto, Department of Electrical Engineering, Toronto, Ontario, M5S 3G4, 1990.
Co-supervised with Glenn Gulak.