UT Nios
UT Nios is a soft-core processor based on the Nios architecture from Altera Corporation.
Please note that this architecture is the first generation of the Nios
processor, NOT Nios II !
A detailed description of the UT Nios processor is given in the master's thesis: Soft-Core Processor Design.
UT Nios Verilog source code is available for download here.
UT Nios is neither associated with, nor supported by Altera Corporation!
The performance of UT Nios was evaluated using the UT Nios benchmark set.
The benchmark set is available for download here.
Both the UT Nios processor, and the UT Nios Benchmark Set are distributed under the terms of the GNU General Public License Version 2.
This means that the code comes WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
Bug reports are welcome, but there is NO SUPPORT GUARANTEED.
Comments and bug reports should be sent to:
plavec@eecg.toronto.edu,
with
subject line "UT Nios Comment/Bug Report".
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