Kerneltron: Massively Parallel Support Vector "Machine" in Silicon
The Kerneltron, a massively parallel VLSI array processor for kernel-based pattern recognition, and the first Support Vector Machine in silicon (Genov and Cauwenberghs, 2001). The core contains an array of CID/DRAM cells, unit memory cells each with a dedicated processor performing binary multiplication and analog accumulation. The array achieves an energy efficiency (operations per unit energy, or throughput over power) and integration density (throughput per unit area) a factor 100-10,000 better than the most advanced multiscalar processors available today. The processor is internally analog and externally digital, combining the best of both worlds: the efficiency of analog computing, and the flexibility of a reconfigurable digital interface. Roman Genov and Gert Cauwenberghs, "Charge-Mode Parallel Architecture for Matrix-Vector Multiplication," IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, vol. 48 (10), pp. 930-936, 2001.
Roman Genov, Shantanu Chakrabartty and Gert Cauwenberghs, Silicon Support Vector Machine with On-Line Learning," Int. J. Pattern Recognition and Artificial Intelligence, 2003 (special issue on SVM'2002).