GENOV’s LAB OPENINGS (as of Feb. 2020)
Advantages of the City of Toronto and the
University of Toronto
FOR UNDERGRADUATE and M.Eng. STUDENTS:
(USRA/UTEA, ECE2500 M.Eng.
Projects, ESC499 Eng Sci Thesis Projects, Design Projects, Volunteering Projects)
SPECIFIC PROJECT OPENINGS FOR
UNDERGRADUATE AND MEng STUDENTS in 2020
Please follow application instructions for each project
posted at the above link. In the subject line of your email message, please
include keywords: “MEng Project Application” or “USRA Summer Project
Application”.
FOR GRADUATE STUDENTS AND POST-DOCTORAL FELLOWS:
Please attach your CV/resume (WITH GPA STATED), your
transcript (in pdf format) and list of the projects below (with project number
and title included) in the order of your preference (highest first).
Starting dates are May or Sept. of
2020-2021, or on a rolling basis any time of the year. Most of the openings listed below are available immediately but not all
may be filled. If you are looking to apply for a PhD
degree or post-doctoral studies please contact me by email directly. The general application process is outlined
at https://www.ece.utoronto.ca/graduates/admission/
Our positions are very competitively funded.
1.
(NEW!) Transport-aware 3D Image Sensors and Cameras for Next-generation
Smart Phones, Autonomous Vehicles, Machine Vision and Artificial Vision (two positions,
collaboration with Prof. Kyros Kutulakos in the Computer Vision Group as well
as with Carnegie Mellon University Robotics Institute and Stanford
Computational Imaging Lab)
The main goal will be to study, design,
and deploy a new class of computational cameras whose key property is that they
are "transport-aware." Unlike conventional cameras which record all
incident light, transport-aware cameras can be programmed to block some of that
light, based on the actual 3D paths it followed through a scene.
Transport-aware cameras use a programmable light source for illumination and a
programmable sensor mask for imaging, and are a pioneering breakthrough in the
fields of computational photography
and computer vision, with diverse
novel applications, as unimaginable as 3D
imaging outdoors, seeing against the sun, around the corner and seeing through
skin!
Live video from a transport-aware camera
can offer a very unconventional view of our everyday world in which refraction
and scattering can be selectively blocked or enhanced, visual structures too
subtle to notice with the naked eye can become apparent, and object surfaces
can be reconstructed in 3D under challenging conditions well beyond the state
of the art.
These
capabilities will find new uses in many industrial, scientific and commercial
applications such as: augmented and virtual reality (for gesture recognition
and object recognition), self-driving cars, 3D printers and scanners, video
games, biomedical imaging systems (such as endoscopy), material analysis,
drones, robots, and industrial machine vision.
The
applicants should have interest and ideally previous experience in some of the
following areas (position 1 covers 1.1, 1.2, 1.3, 1.6 and position 2 covers
1.3, 1.4, 1.5, 1.6)
1.1
CMOS analog
and mixed-signal integrated circuits/systems design (e.g., pixel design, CMOS imager
circuits such as column-parallel readout amplifiers and analog-to-digital
converters (ADCs)),
1.2
Semiconductor device physics: understanding of device physics of
photodetectors as well as their 3D structure photo-generated charge simulation
and layout (e.g., pinned photodiode, photonic mixer device);
1.3
CMOS image sensor experimental
characterization using
our state-of-the art IC testing facilities both in Prof. Genov’s and Prof.
Kutulakos’ labs.
1.4
Digital systems for computer vision: computer architecture and
microprocessor IP on-chip instantiation and programming (e.g., using open-core
microprocessor IP such as TI MSP430 or ARM);
1.5
Embedded systems for computer vision: solid knowledge of Verilog and/or
other hardware description languages for designing top-level camera
architectures (e.g., design and programming of high-date-rate I/O interfaces
such as memory IP interfaces such as DDR2/3/4, USB3 interface, Xilinx
Microblaze Embedded Processor, XIlinx SPI interface protocol, FPGA programming
tools such as by Xilinx or Altera);
1.6
3D cameras deployment at world’s top computer vision
centers (such as collaborators cites at Stanford, Carnegie Mellon University and Rice University).
This
is a highly collaborative project with several research groups around the world
(USA, Italy), including those specializing in photodetector design,
time-of-flight imaging, computer vision, and robotics. There may be
opportunities to travel internationally to top research centers in North
America, Europe and Japan.
2.
(NEW!) E-PHYS: Brain-chip Interfaces/Neurostimulators for
Diagnostics/Treatment of Neurological Disorders (collaborations
with Profs. Taufik Valiante, Peter Carlen, Paul Yoo).
Most of these projects involve implantable and/or wearable CMOS analog
integrated circuits/systems design for neuro-electrical signal
acquisition, filtering and amplification (electrophysiology), ADC/DAC design,
on-chip signal processing, RF communication (transceivers), inductive powering,
electrical neurostimulation, interfacing with brain-implanted high-count
microelectrodes, integration/interfacing with on-chip and off-chip microelectrodes,
and in vivo experimentation with animals.
a. Embedded systems design for
wearable brain interfaces (using
commercially available IC components)
b. Implantable wireless integrated
circuits for brain neural activity monitoring and modulation
c. Wireless brain implants with
on-chip artificial intelligence (including studying machine
learning algorithms and mapping them onto integrated circuits for on-line data
classification and pattern recognition in neural recordings – this is
collaborative with our AI-oriented team members)
d. Brain implants for optogenetic stimulation
(using hybrid integration of electronics and photonic lasers, etc)
e. Selected topics in neuroscience, neurology,
neurosurgery, electrophysiology, animal neurosurgery, epileptology (experience or
interest in electrical engineering and electronics is of benefit, but is not a
must)
3.
(NEW!) E-CHEM: Fully-wireless
Single-chip Microsystems for Electrochemical Diagnostics and Therapy, Both In
Vivo and In Vitro (collaborations with Profs. Taufik Valiante, Peter
Carlen, Mike Thompson, Paul Yoo).
Most of these projects involve wearable / implantable / disposable
CMOS analog integrated circuits/systems
design for neuro-/bio-chemical signal acquisition methods such as voltammetry,
amperometry and impedance spectroscopy, signal filtering and amplification,
ADC/DAC design, on-chip signal processing, RF communication (transceivers),
inductive powering, electrical neurostimulation, interfacing with
brain-implanted high-count microelectrodes, integration/interfacing with
on-chip and off-chip microelectrodes, and in vivo experimentation with animals.
a. Circuits and systems for
electrochemical sensing, imaging and modulation of neurochemicals in the brain
(please see our 2016 MDPI Sensors paper and ISSCC 2018 paper for more details).
b. Implantable chips for peripheral
nerve interfaces and electroceuticals (e.g., responsive micro-stimulators)
c. Gas sensors and olfactory sensors
for volatile organic compounds detection in human breath in order to perform
early medical diagnostics
d. High-throughput drug screening
chips - integrated circuits for patch-clamp electrophysiology
4.
(NEW!) Machine Learning ALGORITHMS for Big Data: Brain Signals Analysis
for Therapeutic Adaptive Brain Stimulation (collaboration with
Profs. Taufik Valiante, Stark Draper, and Jeremie Lefebvre)
Responsive electrical neurostimulation is an emerging technology for the
treatment of many brain disorders. In the Intelligent Sensory Microsystems Lab,
we have been developing technologies to prevent seizures by means of responsive
neurostimulation (i.e., stimulating the brain before an upcoming seizure in
order to prevent the seizure from occurring). As part of this project, we have
been collecting multi-terabyte datasets of clinical intracranial EEG recordings
from patients being evaluated for epilepsy surgery. We are looking for
talented, highly motivated individuals to help us analyze these data.
Specifically, the candidate will develop machine learning algorithms for
predicting the onset of seizures, detecting epileptogenic brain regions and for
identifying optimum brain stimulation strategies. The following qualifications
are required / preferable:
-
Experience with artificial intelligence / machine learning algorithms
(e.g., support vector machines, RNNs, deep learning, boosting, ensemble
methods)
-
Strong programming skills in MATLAB or Python
-
Experience with analyzing time series data
-
Experience with streaming data analysis
-
(Preferably) experience with electrophysiology data
-
(Preferably) experience with C and parallel programming (e.g., MPI)
5.
(NEW!) At-the-edge Digital
Machine Learning VLSI ACCELERATORS for Energy-efficient Brain State
Classification and Responsive Stimulation (collaboration with
Prof. Taufik Valiante and Prof. Naveen Verma at Princeton)
Implementation of energy-efficient machine learning algorithms for both:
(a) accurate prediction/detection of pathological brain states such as
epileptic seizures; and (2) patient-tailored lifelong adaptive neurostimulation.
The algorithms are currently support vector machines and will likely also
include reinforcement learning / RNNs / deep learning etc in the future. These
would be initially implemented on an FPGA connected in a closed loop to a
human patient brain, with a digital ASIC implementation constraints in
minds. Next these would be synthesized on a low-power implantable ASIC. This is
currently a fully-digital computing architecture: on-FPGA/on-ASIC open-core
microprocessor MSP430 IP combined with accelerator co-processors both for
multiple feature extractors and the data classifier, as well as on-chip SRAM,
etc. Please see our ISSCC 2018 for more details (in collaboration with
Princeton). The project involves fully-digital computing architectures (on-chip
microprocessors such as open-core MSP430 IP combined with accelerator co-processors, highly parallel accelerators,
bit-level processing, asynchronous processors, etc) - first in Verilog/FPGA
then fabricated in digital CMOS; novel ways of implementing both feature
extraction (spatio-temporal filtering, PCA, ICA, etc) and data classification
in VLSI; resources balancing between feature extraction and data
classification. We are in the early phase of a 5-year clinical study of
artificially-intelligent responsive brain stimulation to treat intractable
epilepsy that aims to utilize this technology.
6.
Two Projects on
Mixed-signal VLSI Machine Learning Accelerators
6.1 (NEW!) Analog
Integrated Circuits for Bio-Inspired Memristor-Accelerated Machine
Learning-In-Memory for Medical/Implantable Applications (two positions,
collaboration with Prof. Dominique Drouin at Laval University)
The modern world continues to become more interconnected with more and
more sensors coming online. Novel computing systems are much needed to handle
“big” heterogeneous and unstructured data processing. Since conventional
systems are fundamentally not adapted to this class of problems, alternative
solutions are envisioned and demand a complete shift in the computing paradigm,
architecture and technology. To this end, the bio-inspired computing models are
a promising solution to conventional computing since these systems can manage
multi-sensory inputs with a very large bandwidth in real time and with low
energy consumption. Along these lines, artificial neural networks have
experienced renewed interest in recent years, outperforming humans in visual
recognition tasks and gaming. Nevertheless, such systems would benefit
immensely from a dense, parallel and distributed memory (synapses) along the
computing nodes (neurons). In this project we will build an efficient and
versatile system for the future development of machine learning hardware. We
will implement a scalable, flexible and innovative strategy for the
implementation of the synaptic weight and the associated multiply and
accumulate (MAC) operation, one of the most demanding operations for efficient
ML hardware. We will achieve on an optimum balance between CMOS flexibility
/performance and the density/energy efficiency of computation in emerging
memory devices (resistive memory synapses). This will take place at two levels
of integration: (i) we will use an advanced system-in-package approach in order
to optimize heterogeneous integration of memory devices on CMOS chips. Here, we
will design and fabricate memory chips interconnected via flip-chip technology
on an active interposer which will ensure dynamic signal management and routing
while minimizing memory device variability and preserving CMOS design
flexibility. (ii) We will implement a massively parallel and dense memory array
via multiple passive crossbar interconnection in a system-on-chip strategy.
Active amplification between passive crossbars will enable ultra-high memory
density while preserving optimal control of the memory devices.
a. This project involves mixed-signal
CMOS integrated circuits that enable in-memory computing architectures such as those using RRAM
(resistive RAM), with the focus on densely integrated ADC and DAC design (the
ADCs and DACs will control read and write operations for the RRAM). Topics may
also include massively parallel analog computing architectures, computation in
SRAM / DRAM, charge-domain signal processing, analog-to-information converters,
analog-to-time converters, computational ADCs, multiplying ADCs,
bit-level/bit-serial processing, reconfigurable architectures, and non-uniform
sampling ADCs.
b. Another aspect of this project is
energy-efficient computing architectures relying on memristor arrays for
machine learning algorithms (e.g., support vector machines, deep learning,
boosting, ensemble methods)
Some travel to (a beautiful and
one of the oldest cities in North America) Quebec City may be expected.
6.2 (NEW!) Kerneltron-2:
Next-generation Charge-domain Mixed-Signal Machine Learning Accelerator with
In-memory Computing (collaboration with Prof. Gert Cauwenberghs at UCSD,
San Diego).
This project builds on our past success with Kerneltron processor which set a record for energy efficiency
in computing high-dimensional linear transforms. Kerneltron performs computing
directly in memory, so energy or time are not wasted on auxiliary memory
storage, memory access and data communication. The next-generation processor
will utilize a new massively-parallel architecture, an advance technology node
(22nm or better) and a new embedded memory technology (DRAM, NVRAM), all well suited
for accelerating deep neural networks (DNNs) and convolutional neural networks
(CNNs) at the edge. Visits to San Diego are possible/likely. The following qualifications are preferred:
-
Experience in the mixed-signal circuit design (such as ADC design)
-
Some experience in memory circuits design (such as embedded NVRAM / DRAM
/ SRAM, sense amplifiers, SERDES, high-speed I/O etc)
-
Understanding of advanced CMOS nodes (such as 22nm CMOS or SOI process)
-
Knowledge of machine learning algorithms (DNN, CNN, backpropagation, etc)
-
Residence/citizenship of a country where access to an advance technology
node is allowed
-
Availability to travel to San Diego
7.
(NEW!) Server-side/In-cloud
Machine Learning VLSI ACCELERATORS (collaboration with
Prof. Andreas Moshovos)
This project involves digital ASIC
design for implementing high-throughput processor architectures for deep
learning acceleration developed in Prof. Andreas Moshovos group. We aim to
implement his group’s recent advances in processor architecture in custom
silicon. One example of such a processor architecture innovation can be found
in:
J. Albericio, A. Delmás, P. Judd, S. Sharify, G. O’Leary, R. Genov, A.
Moshovos , “Bit-pragmatic Deep Neural Network Computing,” 50th Annual IEEE/ACM
International Symposium on Microarchitecture, Boston, Oct. 2017.
The project includes feasibility study, architecture-to-ASIC translation/mapping,
synthesis and place and route including memory compiler, IC fabrication and
testing. The aim is to submit a manuscript to ISSCC.
8.
(NEW!) Implantable Electrophysiology: Deployment of State-of-the-Art
Intracranial EEG Recording and Neruostimulation Systems in Rodent Models of
Neurological Disorders (in collaboration with
Profs. Taufik Valiante, Paul Yoo and Peter Carlen at the School or Medicine /
Toronto Western Hospital)
We are looking for a graduate student who is interested in a project involving
custom design and neurosurgical implantation
of novel intracranial EEG microelectrodes (from Genov) into animal models
of disorders of the central (Valiante, Carlen) and peripheral (Yoo) nervous
system. The student may also perform signal processing of the EEG signals to
study the signal characteristics of the EEG from an animal model of a
neurological disorder and the effects of treatment. The student would be
expected to become skilled and independent for
electrophysiological experimentation, and to interface between
several collaborating labs.
OTHER ONGOING PROJECTS
WITH PERIODIC VACANCIES:
9.
Analog and Mixed-Signal
Integrated Circuit Design for Next-Generation Brain-Chip, Skin-Chip and Other
Organ-Chip Interfaces
a. Oversampling and Nyquist-rate
analog-to-digital converters (please see our JSSC 2016 and ISSCC 2017, 2018
papers for examples of previous designs)
b. Analog-to-digital converter arrays for sensory
applications
c. Computational analog-to-digital converters /
information-to-digital converters
d. Analog-to-digital converters for non-uniform /
compressive data sensing
e. Analog signal processing, including
digitally-assisted analog design
f. Analog-digital co-design / mixed-signal
systems-on-chip
10. Opto-electronic Implantable, Wearable and Disposable Integrated
Circuits (CMOS Imagers) for Optogenetic Photonic Stimulation and
Bio-sensing/Neuro-imaging
a. Implantable wireless CMOS contact imagers for
optical monitoring of brain activity
b. Optical biosensors – fluorescence, bio- and
chemi-luminescence CMOS contact imagers
c. CMOS optical DNA microarrays - wireless
integrated circuits for on-chip fluorescent DNA analysis
(including spectrum sensing photosensor arrays design, sensory
information acquisition circuit design, ADC/DAC design, on-chip mixed-signal
VLSI signal processing, RF transceiver circuits, high-voltage CMOS circuit
design, post-CMOS on-chip microelectrode fabrication and integration with
microfluidic/photonic structures).
11. Wireless RF Integrated
Circuit Design for Implantable, Injectable, and Wearable-patch Health Monitors
and Neurostimulators
a. Low-power transmitter and receiver design
(e.g., UWB / pulse radio design)
b. Implantable / wearable (eg. body-area) /
disposable transceivers design
c. RFIC, RFID and antenna design
d. Antenna design (including on-chip antennas and
coils) and high-frequency PCB design
Most positions are in ECE,
ECE-IBBME Collaborative Program, or IBBME.
If you have received/applied for a NSERC or OGS graduate scholarship or have
another funding source, please inform me of this.
Most of the
projects are collaborative, with participants from multiple other disciplines,
mainly in Medicine, Neuroscience, Chemistry, Molecular Biology, Cell Biology, Computer
Vision and Robotics. Unique opportunities exist for joint
student supervision with other faculty members in Electrical and Computer
Engineering (Electromagnetics – with Prof. George Eleftheriades, Photonics –
with Prof. Joyce Poon), in IBBME (Neural Engineering – with Prof. Paul Yoo,
Neurosurgery/Neuroscience – Prof. Taufik Valiante, Neurology/Neuroscience –
Prof. Peter Carlen and others) and those in other departments (Computer
Science/Vision – Prof. Kyros Kutulakos, Chemistry/Sensors – Prof. Michael
Thompson, Medicine, Collaborative Program in Neurosciences, Institute of
Medical Science, etc).
Please note
that the training focus in our lab is on academic careers (future
professorships), entrepreneurship (future co-founders and CTOs/CEOs of companies)
and senior-level R&D positions in industry worldwide. For most of the listed positions we prefer applicants with excellent
communication skills who take initiative, and who are proven leaders,
problem-solvers, self-starters, and team players.
Qualified
students interested in joining our lab are encouraged to apply for admission
into our Ph.D. or M.A.Sc. degree programs as well as the post-doctoral stream.
Applicants with a Bachelor degree can enroll directly into the Ph.D. program
immediately or upon successful completion of the first two semesters of
studies. Admitted students generally receive full financial support for the
duration of their studies. The general
application process is outlined at https://www.ece.utoronto.ca/graduates/admission/
You can also
contact me, Prof. Roman Genov, by email at roman[AT]eecg.utoronto.ca. Please
attach your CV/resume in pdf format (with GPA clearly stated) and your
transcript. Sometimes I am not able to answer all email inquiries but will keep them
on file until the graduate office or our team has received all of your
application materials.
