ECE 1388 Final Project
Frame Synchronizer
Sylvia Cheung
Dec. 20 2006
1 System Outline
1.1 General
Frame synchronizers are commonly used in communication systems and video circuit applications. The frame synchronizers help aligning the data frames through a pre-defined frame synchronization pattern specific to that system, and report errors when data transmissions fail or are delayed.
The frame synchronization pattern is found at the end of a data frame, after the data payload. The synchronization pattern is used to signal the end of a frame.
Our project is to build a frame synchronizer, as shown in Figure 1, which demonstrates not only the basic of the synchronization functionality as mentioned above, but also some advanced features which include:
w Let users define the specific frame synchronization pattern
w Output the data payload contained in a data frame word by word
w Identify each outputted data word with a unique key encoded in Gray code. This helps the external systems to manipulate the received data word for their own purposes
Figure 1 System Overview
1.2 System Specification
Our Frame Synchronizer uses 0.35um technology and it operates up to 50MHz.
1.2.1 Data Frame Format
In our system, a data frame contains eight words. Each word is 16-bit long. The first seven words are data which corresponds to some pieces of information. The last word is the frame synchronization pattern that indicates the end of the data frame.
Figure 2 Data Frame
1.3 Pin Specification
Our Frame Synchronizer contains 19 inputs and 20 outputs. The pin configuration and the pin assignment of the Frame Synchronizer are summarized below:
|
Pin Name |
Direction |
Description |
|
vdd! |
|
Power Supply - VDD |
|
gnd! |
|
Power Supply - GND |
|
clk |
In |
Clock signal |
|
reset |
In |
Reset signal, active high |
|
data |
In |
Serial data frames |
|
sp[0..15] |
In |
Frame Synchronization Pattern (16-bit) |
|
out[0..15] |
Out |
16-bit data stored in the data frame |
|
mkey[0..2] |
Out |
Data Key (implemented in Gray code) identifying each data word (out[0..15]) in a data frame that outputs to some external system |
|
lock |
Out |
Lock signal, active high, indicating if the system has been synchronized |
Table 1 Pins Configuration
|
Pin Number |
Pin Name |
Pin Number |
Pin Name |
|
1 |
sp6 |
21 |
lock |
|
2 |
sp7 |
22 |
out8 |
|
3 |
sp8 |
23 |
out7 |
|
4 |
sp9 |
24 |
out6 |
|
5 |
sp10 |
25 |
out5 |
|
6 |
sp11 |
26 |
out4 |
|
7 |
sp12 |
27 |
out3 |
|
8 |
sp13 |
28 |
out2 |
|
9 |
sp14 |
29 |
out1 |
|
10 |
sp15 |
30 |
gnd |
|
11 |
out15 |
31 |
out0 |
|
12 |
out14 |
32 |
vdd |
|
13 |
out13 |
33 |
data |
|
14 |
out12 |
34 |
clk |
|
15 |
out11 |
35 |
reset |
|
16 |
out10 |
36 |
sp0 |
|
17 |
out9 |
37 |
sp1 |
|
18 |
mkey1 |
38 |
sp2 |
|
19 |
mkey0 |
39 |
sp3 |
|
20 |
mkey2 |
40 |
sp4 |
|
|
|
41 |
sp5 |
Table 2 Pins Assignment
The pins are arranged in a square pad. The figure below shows the chip layout.
Figure 3 Chip Layout
1.4 Files Location
The schematics, the layouts and the extracted files of all the components implemented for Frame Synchronizer project are located under:
/nfs/eecg/homes/meng/wongsta1/FinalDelivery
The schematics, the layouts and the extracted files of the core with the pad frame are located under:
/nfs/eecg/homes/meng/scheung/padframeLib
2 Design
The Frame Synchronizer is
represented by five main modules: shift register, a comparator, a 7-Bit Counter
and its logic, a FSM, and an output buffer.
The functionalities of each module are described in the following
sections.
2.1 Shift Register
The 16-bit shift register is
responsible for holding the current bit and the previous 15 bits in every clock
cycle. It has 1 data input and 16 outputs. The 16-bit outputs connect to both
the comparator and the output buffer.
The shift register is composed of
16 D-type master-slave positive-edge triggered flip-flops in series. The
following shows the schematics and the layout of the 16-bit shift register.
Figure 4 16-bit Shift Register Schematic
Figure 5 16-bit Shift Register Layout
The following timing diagram shows that the data (din) is being shifted one bit at every positive edge of a clock cycle, after being reset (rb) at the first clock cycle. 16 bits (d[0..15]) are being outputted.
Figure 6 16-bit Shift Register Timing Diagram
2.1.1 DFF
A flip-flop consists of eight
NAND gates and two inverters. The flip-flops are positive-edge triggered and
asynchronous. The following shows the
schematics and layout for a DFF.
Figure 7 Asynchronous D-type Flip-flop Schematic
Figure 8 Asynchronous D-type Flip-flop Layout
The following timing diagram shows that the behaviour of the positive-edge triggered D-type Flip-flop.
Figure 9 Timing diagram of an asynchronous D-type Flip-flop
2.2 Comparator
The comparator serves the purpose
of comparing the last 16-bit of the 128-bit data frame with the user-defined 16
bits synchronization pattern. The output, match signal, is high when the two
patterns are matched. The matching
process of the data coming from the shift register and the user-defined
synchronization pattern does not depend on any clock cycle.
The comparator is made up of 16
XNOR gates and 15 AND gates. The comparison is done bit by bit using XNOR. The following figure shows the schematics and
layout of the comparator.
|
|
|
Figure 10 Comparator Schematic and Layout
The layout is arranged as 16 rows and each row consists of an XNOR gate and an AND gate, except the last row, which only an XNOR gate is present. The following figure shows one typical row in the comparator.
Figure 11 One Typical Row in the Comparator
The following timing diagram
shows that the match signal becomes low when the user-defined synchronization
pattern (/vary) is changed.
Figure 12 Comparator Timing Diagram
2.2.1 XNOR
XNOR is implemented using NAND gates and inverters. The following
shows the schematics and layout for an XNOR.
Figure 13 XNOR Schematic
Figure 14 XNOR Layout
2.3 7-Bit Counter and its Logic
The 7-Bit Counter and its Logic consist of: a 7-Bit Counter, logic to indicate it is at 16th or its multiple clock cycle/bit, and logic to indicate it is at 128th clock cycle/bit.
2.3.1 7-Bit Counter
The 7-Bit Counter is for counting up to 128th
clock cycle/bit. It is made up of master
slave negative-edge triggered JKFFs and some AND
gates. The following shows the schematics and layout
for the 7-Bit Counter.
Figure 15 7-Bit Counter Schematic
Figure 16 7-Bit Counter Layout
The following timing diagram shows how each bit changes for every clock cycle at its negative edge, after resetting at the first clock cycle.
Figure 17 7-Bit Counter Timing Diagram
2.3.1.1 Master Slave Negative-edge Triggered JKFF
The following shows the schematics and layout for the master slave JKFF.
Figure 18 JKFF Schematic
Figure 19 JKFF Layout
The following timing diagram
shows that the behaviour for the master slave
JKFF.
Figure 20 JKFF Timing Diagram
2.3.2 logicEvery16Bits Module
The logicEvery16Bits component outputs a high enable signal at every 16 clock cycle. This is achieved by monitoring the 4 least significant bits from the counter and when they are all high, it is at the cycle of 16th or its multiples.
16bitEnable = P0 P1 P2 P3
The following shows the schematics and layout for the logicEvery16Bits module.
Figure 21 logicEvery16Bits Schematic
Figure 22 logicEvery16Bits Layout
2.3.3 logicLast16Bits Module
The logicLast16Bits component outputs a high sample signal at the last 16th clock cycle of the total 128th clock cycle. This is achieved by monitoring the 3 most significant bits from the 7-Bit Counter with the enable signal from the logicEvery16Bits. When they are all high, it is at the last 16th clock cycle.
sample = 16bitEnable P4 P5 P6
= 16bitEnable last16Bits
The following shows the
schematics and layout for part of the logicLast16Bits module.
Figure 23 Part of the logicLast16Bits Module Schematic
Figure 24 Part of the logicLast16Bits Module Layout
2.3.4 Overall 7-Bit Counter and its Logic
The following shows the schematics and layout for the overall 7-Bit Counter and its Logic.
Figure 25 7-Bit Counter and its Logic Schematic
Figure 26 7-Bit Counter and its Logic Layout
The following timing diagram shows how the signal 16bitEnable becomes high during the 16th and its multiple clock cycle (controlled by the 3 most significant bits of the 7-bit output from the counter). The signal sample also becomes high during the last 16th bit of the 128-bit clock cycle.
Figure 27 7-Bit Counter and its Logic Timing Diagram
2.4
Output Buffer
The Output Buffer serves two purposes: outputting the serial data in a parallel fashion (16 bit) and outputting the gray-coded Data Key to let the users know which data packet they are receiving.
2.4.1 Serial-to-parallel Data Component
This component is responsible for outputting 16-bit data. It is made up of 16 transmission gates and is controlled by the 16bitEnable signal which is generated by the 7-Bit Counter and its logic.
2.4.1.1 Transmission Gate
The following shows the schematic
and layout of a transmission gate:
Figure 28 Transmission Gate Schematic
Figure 29 Transmission Gate Layout
The timing diagram below shows that when the transmission gate is enabled, the output (out) will follow the input (in).
Figure 30 Transmission Gate Timing Diagram
2.4.2 logicMKey Module
This component is responsible for outputting the corresponding Data Key at the negative edge of the 16 and its multiples clock cycles. The gray-coded Data Key is used and is listed below:
|
Input Data Packet Number |
Input Data Packet Number (in Binary) |
Output Data Key using Gray Code (in Binary) |
|
|
P6 P5 P4 |
out2 out1 out0 |
|
#1 |
000 |
001 |
|
#2 |
001 |
011 |
|
#3 |
010 |
010 |
|
#4 |
011 |
110 |
|
#5 |
100 |
111 |
|
#6 |
101 |
101 |
|
#7 |
110 |
100 |
|
#8 (Synch Pattern ) |
111 |
000 |
Table 3 Gray Code Representation
In this component, the following logics are implemented using the 3 most significant bits of the 7-bit counter. Change occurs in the 3 most significant bits every 16 clock cycles, so as the Data Key should be.
out2 = /P6 P5 P4 + P6 /P5 + P6 /P4
= / ( ( / ( P4 P5 /P6 ) ) ( / ( / (P4 P5) P6 ) ) )
out1 = /P6 P4 + /P6 P5 + P6 /P5 /P4
= / ( (/ (/
( /P4 /P5 ) ) /P6 )
(/ ( /P4 /P5 P6 ) ) )
out0 = /P5
Note: / means the negated signal
The schematic and the layout of logicMKey are shown below:
Figure 31 logicMKey Schematic
Figure 32 logicMKey Layout
The timing diagram for this logicMKey is contained in the one for FSM.
2.5 FSM
FSM is responsible for generating the lock signal. The lock signal indicates if the frame synchronization pattern extracted from the input data stream locks in (matches) with the user-defined one: there are two states for lock signal: 0 and 1. In the system’s view, the lock signal can be a signal to indicate that the data is ready to be used by the system.
Basically, when it is time to sample the synchronization pattern (at the 128 clock cycle when the whole synchronization pattern has already received) and the match signal indicates that the synchronization pattern in the data stream matches with the user-defined one, the lock will become 1 at the negative edge of that cycle. If it does not match, the lock will become 0. The lock will remain the same until the next sampling time (another 128 clock cycles).
FSM is a measly state machine and is implemented according to the following truth table using the sample and match signals generated from comparator, and 7-bit counter and its logic:
|
sample (S) |
match (M) |
|
|
lock (L) |
|
0 |
0 |
0 |
0 |
0 |
|
1 |
0 |
0 |
0 |
0 |
|
0 |
1 |
0 |
0 |
0 |
|
1 |
1 |
0 |
1 |
1 |
|
0 |
0 |
1 |
1 |
1 |
|
1 |
0 |
1 |
0 |
0 |
|
0 |
1 |
1 |
1 |
1 |
|
1 |
1 |
1 |
1 |
1 |
Table 4 FSM Truth Table
L = S M /Q + /S /M Q + M Q
Negative-edge triggered JK flip flop is used to produce the set or reset functionalities by having inverting inputs of lock for J and K. The JKFF is designed to be negative-edge triggered so that there is enough time for the match signal to get ready during the first half clock cycle.
The following shows the schematics and layout for FSM.
Figure 33 FSM Schematic
Figure 34 FSM Layout
The following timing diagram shows that two testing scenarios (highlighted by the vertical markers):
- When it is time to sample, but the extracted synchronization pattern does not match with the user-defined one, the lock becomes low.
- When it is time to sample, and the extracted synchronization pattern matches with the user-defined one, the lock becomes high.
Figure 35 FSM Timing Diagram
2.6 Complete Circuit
The following shows the schematics and layout for the complete circuit.
Figure 36 Complete Circuit Schematic
Figure 37 Complete Circuit Layout
The following timing diagram shows how the data key is outputted every 16th clock cycle according to the gray code. It also shows that the lock signal becomes high at the last 16th clock cycle of the total of 128 clock cycles.
Figure 38 Complete Circuit Timing Diagram
2.7 Core in the Pad Frame
The pad frame uses PADIN (for input pins), PADOUT (for output pins), PADPROTCAPVDD (for power supply Vdd) and PADPROTGND (for power supply Gnd). The following shows the schematics and layout for core with the squared pad frame.
Figure 39 Core with the Pad Frame Schematic
Figure 40 Core with the Pad Frame Layout
3 Area
The following table shows the area for each component and its total area.
|
Component |
Area (um x um) |
|
Shift Register |
50 x 224 |
|
Comparator |
45 x 224 |
|
7-Bit Counter and its Logic |
82 x 182 |
|
FSM |
22 x 182 |
|
Output Buffer |
14 x 202 |
|
Core in the Pad Frame |
1240 x 1296 |
Table 5 Areas for Each Component and its Total Area
4 Tasks Division
|
Task |
|
Sylvia |
|
System Specification and Design |
X |
X |
|
Design, Schematic and Unit Testing |
|
|
|
Shift Register |
X |
|
|
Comparator |
|
X |
|
7-Bit Counter and its Logic |
|
X |
|
Output Buffer |
|
X |
|
FSM |
|
X |
|
Complete Circuit |
|
X |
|
Core with the Pad Frame |
|
X |
|
|
||
|
Layout and LVS |
|
|
|
Shift Register |
X |
|
|
Comparator |
X |
|
|
7-Bit Counter and its Logic |
|
X |
|
Output Buffer |
X |
|
|
FSM |
|
X |
|
Complete Circuit |
X |
|
|
Core with the Pad Frame |
X |
X |
Figure 41 Tasks Division
5 LVS Report
The following is the LVS report for the core with the pad frame:
@(#)$CDS:
LVS version 5.0.0 08/17/2004 10:15 (cds12107) $
Command
line: /nfs/vrg/cmc/cmc/tools/cadence.2003a/IC5033USR3/tools.sun4v/dfII/bin/32bit/LVS
-dir /nfs/eecg/homes/meng/scheung/LVS -l -s -t /nfs/eecg/homes/meng/scheung/LVS/layout /nfs/eecg/homes/meng/scheung/LVS/schematic
Like
matching is enabled.
Net
swapping is enabled.
Using terminal names as correspondence points.
Net-list summary for /nfs/eecg/homes/meng/scheung/LVS/layout/netlist
count
989 nets
41 terminals
968 nfet
81 diode
1 capacitor
1046 pfet
Net-list summary for /nfs/eecg/homes/meng/scheung/LVS/schematic/netlist
count
989 nets
41 terminals
968 nfet
81 diode
1 capacitor
1046 pfet
Terminal correspondence points
N641
N29 clk
N581
N61 data
N529
N1 gnd!
N417
N60 lock
N1056
N93 mkey0
N26 N37
mkey1
N647
N36 mkey2
N600
N77 out0
N935
N54 out1
N1394
N62 out10
N1180
N32 out11
N1335
N95 out12
N1022
N53 out13
N166
N88 out14
N1142
N85 out15
N967
N100 out2
N30
N40 out3
N672
N64 out4
N800
N91 out5
N317
N52 out6
N761
N50 out7
N1042
N74 out8
N568
N51 out9
N444
N11 reset
N470
N46 sp0
N1079
N17 sp1
N971
N6 sp10
N71
N82 sp11
N446
N12 sp12
N437
N99 sp13
N1268
N22 sp14
N509
N96 sp15
N466
N39 sp2
N1277
N35 sp3
N786
N69 sp4
N995
N23 sp5
N941
N63 sp6
N77
N86 sp7
N855
N56 sp8
N633
N20 sp9
N701
N0 vdd!
The
net-lists match.
layout schematic
instances
un-matched 0 0
rewired 0 0
size errors 0 0
pruned 0 0
active 2096 2096
total 2096 2096
nets
un-matched 0 0
merged 0 0
pruned 0 0
active 989 989
total 989 989
terminals
un-matched 0 0
matched but
different type 0 0
total 41 41
Probe
files from /nfs/eecg/homes/meng/scheung/LVS/layout
devbad.out:
netbad.out:
mergenet.out:
termbad.out:
prunenet.out:
prunedev.out:
audit.out:
Probe
files from /nfs/eecg/homes/meng/scheung/LVS/schematic
devbad.out:
netbad.out:
mergenet.out:
termbad.out:
prunenet.out:
prunedev.out:
audit.out:
Probe
files from /nfs/eecg/homes/meng/scheung/LVS/layout
devbad.out:
netbad.out:
mergenet.out:
termbad.out:
prunenet.out:
prunedev.out:
audit.out: