Welcome to my "old" academic website.

My name is Sean Safarpour and I received my Ph.D. from the University of Toronto in Computer Engineering. I am currently with Vennsa Technologies, but I am still very much involved with research at the University of Toronto.

Here is a list of my publications.

- Sean Safarpour and Andreas Veneris, "Automated RTL Debugging with Functional and Hierarchical Abstraction," in IEEE International High Level Design Validation and Test Workshop (HLDVT), San Francisco, 2009. Invited paper

- Sean Safarpour and Andreas Veneris, "Automated Design Debugging with Abstraction and Refinement," in IEEE Transactions on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems (TCAD), in print, 2009.

- Yibin Chen, Sean Safarpour and Andreas Veneris, ``Optimal Trace Compaction with Property Preservation,'' in IEEE Midwest Symposium on Circuits and Systems, Cancun, Mexico, 2009

- Andreas Veneris and Sean Safarpour, ``The Day Sherlock Holmes Decided to do EDA,'' in IEEE/ACM Design Automation Conference (DAC), San Francisco, CA, 2009. Invited paper

- Andrew C. Ling, Stephen Dean Brown, Jianwen Zhu, Sean Safarpour, "Towards automated ECOs in FPGAs," International Symposium on Field Programmable Gate Arrays, FPGA (FPGA), Monterey, California, 2009

- Yibin Chen, Sean Safarpour , Andreas Veneris, and Joao Marques-Silva, "Spatial and Temporal Design Debug using Partial MaxSAT", IEEE Great Lakes VLSI Symposium (GLSVLSI), 2009

- Sean Safarpour , Andreas Veneris, and Rolf Drechsler, "Improved SAT-based Reachability Analysis with Observability Don't Cares", in Journal on Satisfiability, Boolean Modeling and Computation (JSAT), Volume 5 (2008), pages 1-25. PDF

- S. Safarpour , M. Liffiton, H. Mangassarian, A. Veneris, K. Sakallah, "Improved Design Debugging using Maximum Satisfiability", in Formal Methods in Computer Aided Design (FMCAD), Austin, TX, 2007 PDF

- H.Mangassarian, A.Veneris, S.Safarpour , M.Benedetti and D.Smith, "A Performance-Driven QBF-Based Iterative Logic Array Representation with Applications to Verification, Debug and Test", in Int'l Conference on Computer-Aided Design (ICCAD), 2007

- S. Safarpour , A. Veneris, "Abstraction and Refinement Techniques in Automated Design Debugging", in Design Automation and Test in Europe (DATE), Nice, France, 2007 PDF

- H. Mangassarian, A. Veneris, S. Safarpour , F.N. Najm, M.S. Abadir, "Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability", in Design Automation and Test in Europe (DATE), Nice, France, 2007

- S. Safarpour , A. Veneris, H. Mangassarian, "Trace Compaction using SAT-based Reachability Analysis", in ASP-Design Automation Conference (ASPDAC), Yokohama, Japan, 2007 PDF

- S. Safarpour , G. Baeckler, R. Yuan, A. Veneris, "Efficient SAT-based Boolean Matching for FPGA Technology Mapping", in Design Automation Conference (DAC), San Francisco, USA, 2006 PDF

- S. Safarpour , A. Veneris, R. Drechsler, "Integrating Observability Don't Cares in All-Solution SAT solvers", in International Symposium on Circuit and Systems (ISCAS), Kos, Greece, 2006 PDF

- G. Fey, S. Safarpour , A. Veneris, R. Drechsler, "On the Relation Betweem Simulation-based and SAT-based Diagnosis", in Design Automation and Test in Europe (DATE) Conference, Munich, Germany, 2006

- M. Fahim Ali, S. Safarpour, A. Veneris, M. Abadir, R. Drechsler, "Post-Verification Debugging of Hierarchical Designs", in Int'l Conference of Computer-Aided Design (ICCAD), San Jose, USA, 2005 PDF

- S. Safarpour, G. Fey, A. Veneris, R. Drechsler, "Utilizing Don't Care States in SAT-based Bounded Sequential Problems", in ACM Great Lakes Symposium on VLSI (GLSVLSI), Chicago, USA, 2005 PDF

- J. B. Liu, A. Veneris, S. Safarpour, M. Abadir,"Diagnosing Multiple Transition Faults in the Absence of Timing Information", in ACM Great Lakes Symposium on VLSI (GLSVLSI), Chicago, USA, 2005 PDF

- M. Fahim Ali, A. Veneris, S. Safarpour, R. Drechsler, A.Smith and M.S.Abadir, "Debugging Sequential Circuits Using Boolean Satisfiability", in Int'l Conference of Computer-Aided Design (ICCAD), San Jose, USA, 2004 PDF

- S. Safarpour, A. Veneris, R. Drechsler and J. Lee, "Managing Don't Cares in Boolean Satisfiability", in Design Automation and Test in Europe (DATE) Conference, Paris, France, 2004 PDF