Device modelling and characterization

Current deep submicron MOSFET compact models are inaccurate for RF analog and very high frequency applications. Also, current practice for CMOS model extraction is to rely on DC and low-frequency capacitance measurements on large test structures. It is proposed to develop model extraction techniques for sub-100nm CMOS based on high frequency measurements up to 110 GHz that will improve the RF accuracy of MOSFET compact models.

As semiconductor technologies are moving to 90 nm lithography in 2003 and 65 nm by 2006, these modelling problems will be exacerbated due to quantum effects, large statistical variability of device parameters across and within wafers, and by significant gate leakage.



Figure 1: fT scaling of Si CMOS and SiGe BiCMOS technologies


In addition, the traditional MOSFET will be replaced by novel 3D structures like the FINFET that will likely require significantly different compact models than BSIM3/4 or MM12. It is expected that this research will improve on the physicality of existing models, thus improving the model's process- and geometry scalability and allowing for reliable statistical circuit simulations. New compact models may also have to be developed.





Figure 2: Comparison of the measured high speed characteristic of state-of-the-art Si CMOS, GaAs p-HEMT and InP HEMT field effect transistors.


It is expected that process and geometry scalable compact models for transmission lines,


Figure 3: Transmission line test structures for parameter extraction


multi-layer interconnect,





Figure 4: a) 3D EM simulation test structure and b) extracted coupling capacitances for multilayer interconnect.


and circuit isolation structures, valid up to 110 GHz, will also be investigated. Techniques for automatic extraction of interconnect to capture single and coupled transmission line effects will be developed.


New, low parasitic capacitance and low-loss bonding pads, inductors,




Figure 4: a) Inductor test and de-embedding structures and b) measured vs. simulated inductance and Q as a function of frequency for a 3-terminal, center-tapped inductor.


varactor diodes and MIM capacitor structures will be explored that would allow for operation in the 40 GHz to 110 GHz range on a silicon substrate.




Sorin Voinigescu

September 2002