ECE1373  VLSI Systems Design

No Java Support

 

Course Meeting:  Wed 5 - 7pm.  Classroom: SF2103

 

NDA Form
TSMC 0.35um Phantom Library Access Form

 

Basic TSMC 0.35 CMOS DSM Flow
Phase 1:  Synthesis using Synopsys
Phase 2:  Floorplanning using Physical Design Planner
Phase 3:  Place&Route using Silicon Ensemble
Phase 4:  Full-Timing Simulation and Back-Annotated
Phase 5:  LVS and DRC using Cadence DFII

 

Hierarchical CAD flow

 

Project : ATM Packet-Switching Chip

 

Lecture Slides:
Lec1: CAD Flow Overview and VHDL Coding
Lec2: Partitioning and Synthesis Constraints
Lec3: Clock Modeling and Optimization Methods
Lec4: Hierarchical Compilation and Scan Chain Insertion
Lec5: Pads Insertion and Cadence Design Planner
Lab1: Floorplanning using Cadence PDP
Exercise1:
Exercise Documentation

 

 

FAB and  CAD Tools
TSMC - Taiwan Semiconductor Manufacturing Company, Taiwan
UMC - United Microelectronics Corporation, Taiwan
Cadence
Synopsys
Avanti