SQIP to my (LS)Q: Rethinking Loads and Stores in Out-of-Order Microarchitectures

Concerns about energy efficiency and design/verification effort and a general strategy based on multi-core integration are all pushing towards simpler core microarchitectures. One microarchitectural component that offers a great opportunity for simplification is the load-store queue (LSQ), which is responsible for implementing the functions associated with out-of-order load and store processing. Conventional LSQs are problematic because they rely on both age-ordering (which makes partitioning and multithreading difficult) and associative search (which scales poorly in terms of latency and power consumption) but more so because they are tightly integrated into the execution datapath.

This talk will present two microarchitectures that overcome the drawbacks of a traditional LSQ by moving pieces of its functionality out of the out-of-order core and into the in-order front- and back-end pipelines. The first design, SQIP, relies on accurate memory dependence prediction and re-execution based load verification to eliminate associative search from the LSQ. The second design, NoSQ, exploits speculative memory bypassing (SMB) to remove the LSQ entirely.

This is joint work with Tingting Sha and Prof. Milo Martin.

Bio:

Amir Roth is an assistant professor at the Computer and Information Sciences Department at the University of Pennsylvania, where he co-leads the architecture and compilers group (ACG). His current research focuses on scalable microarchitectures and memory systems for multi-core processors. His current projects include minigraph processors (with Anne Bracy), ON-Core (with Andrew Hilton) and NoSQ (with Tingting Sha and Prof. Milo Martin).

Prof. Roth received a BS in physics from Yale University in 1994 and a PhD in computer science from the University of Wisconsin-Madison in 2001. He received the NSF CAREER award in 2002.


Greg Steffan
Last modified: Thu Feb 22 11:06:33 EST 2007