Greg Steffan Associate Professor & Jeffrey Skoll Chair in Software Engineering ECE, U of Toronto announce Professor Greg Steffan's passing on July 24, 2014.
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Publications (by date)
TILT: A Multithreaded VLIW Soft Processor Family, Kalin Ovtcharov, Ilian Tili, and J. Gregory Steffan, International Conference on Field Programmable Logic and Applications, Porto, Portugal, August, 2013.NetThreads-10G: Software Packet Processing on NetFPGA-10G in a Virtualized Networking Environment, Stuart Byma, J. Gregory Steffan, and Paul Chow, International Conference on Field Programmable Logic and Applications: Demo Night, Porto, Portugal, August, 2013.
Virtualizing FPGA Accelerators for SAVI (poster), Stuart Byma, J. Gregory Steffan, and Paul Chow, SAVI: Smart Applications on Virtual Infrastructure: Annual General Meeting, July, 2013.
TILT: A Multithreaded VLIW Soft Processor Family (poster), Kalin Ovtcharov, Ilian Tili, and J. Gregory Steffan, International Symposium on Field-Programmable Custom Computing Machines, April, 2013.
Compiler Support for Fine-Grain Software-Only Checkpointing, (pdf) Chuck Zhao, Ph.D. Thesis, Department of Electrical and Computer Engineering, University of Toronto, December, 2012.
Caliper: Precise and Responsive Traffic Generator, (pdf, slides.pdf) Monia Ghobadi, Geoffrey Salmon, Yashar Ganjali, Martin Labrecque, and J. Gregory Steffan, IEEE Symposium on High Performance Interconnects, Santa Clara, CA, August, 2012.
Portable, Flexible, and Scalable Soft Vector Processors, (pdf) Peter Yiannacouras, J. Gregory Steffan, and Jonathan Rose, in IEEE Transactions on VLSI, 20 (8) August, 2012.
Compiler Support for Fine-Grain Software-only Checkpointing, (pdf,ppt) Chuck Zhao, J. Gregory Steffan, Cristiana Amza, and Allan Kielstra, in International Conference on Compiler Construction, Tallinn, Estonia, March, 2012.
Octavo: an FPGA-Centric Processor Family, (pdf,pptx) Eric LaForest and J. Gregory Steffan, International Symposium on Field-Programmable Gate Arrays, Monterey, CA, February, 2012.
Multi-Ported Memories for FPGAs via XOR, (pdf,pptx) Eric LaForest, Ming Liu, Emma Rapati, and J. Gregory Steffan, International Symposium on Field-Programmable Gate Arrays, Monterey, CA, February, 2012.
DART: A Programmable Architecture for NoC Simulation on FPGAs, Danyao Wang, Charles Lo, Jasmina Vasiljevic, Natalie Enright Jerger, and J. Gregory Steffan, to appear in IEEE Transactions on Computers, 2012.
Programmer-Assisted Automatic Parallelization, Diego Huang and J. Gregory Steffan, International Conference hosted by the Centre for Advanced Studies Research, Toronto, November, 2011.
Understanding and Improving Bloom Filters for Lazy Transactional Memory, (pdf) Mark Jeffrey, M.A.Sc. Thesis, Department of Electrical and Computer Engineering, University of Toronto, September, 2011.
The Potential for a GPU-Like Overlay Architecture for FPGAs, (html/pdf) Jeffrey Kingyens and J. Gregory Steffan, International Journal of Reconfigurable Computing, September, 2011.
Programmer-Guided Automatic Parallelization, Diego Huang, M.A.Sc. Thesis, Department of Electrical and Computer Engineering, University of Toronto, September, 2011.
Application-Specific Signatures for Transactional Memory in Soft Processors, (pdf) Martin Labrecque, Mark Jeffrey, and J. Gregory Steffan, ACM Transactions on Reconfigurable Technology and Systems, 35 (3) August, 2011.
Understanding Bloom Filter Intersection for Lazy Address-Set Disambiguation, (pdf, ppt) Mark Jeffrey and J. Gregory Steffan, ACM Symposium on Parallelism in Algorithms and Architectures, San Jose, CA, June, 2011.
Overlay Architectures for FPGA-Based Software Packet Processing, (pdf) Martin Labrecque, Ph.D. Thesis, Department of Electrical and Computer Engineering, University of Toronto, June, 2011.
DART: Fast and Flexible NoC Simulation using FPGAs, (pdf, ppt) Danyao Wang, Natalie Enright Jerger, and J. Gregory Steffan, International Symposium on Networks-on-Chip, Pittsburgh, PA, May, 2011.
NetTM: Faster and Easier Synchronization for Soft Multicores via Transactional Memory, (pdf, slides.pdf) Martin Labrecque, J. Gregory Steffan, International Symposium on Field-Programmable Gate Arrays, Monterey, CA, February, 2011.
Parallelizing FPGA Placement Using Transactional Memory, (pdf, ppt) Steven Birk, J. Gregory Steffan, and Jason H. Anderson, International Conference on Field-Programmable Technology, (Best Paper Award), Beijing, China, December, 2010.
The Case for Hardware Transactional Memory in Software Packet Processing, (pdf, pptx) Martin Labrecque and J. Gregory Steffan, ACM/IEEE Symposium on Architectures for Networking and Communications Systems, La Jolla, CA, October, 2010.
An FPGA-based Accelerator Platform for Network-on-Chip Simulation, (pdf) Danyao Wang, M.A.Sc. Thesis, Department of Electrical and Computer Engineering, University of Toronto, September, 2010.
NetThreads Routing Edition: Programming NetFPGA with Threaded Software, Martin Labrecque, J. Gregory Steffan, Geoff Salmon, Monia Ghobadi, and Yashar Ganjali, (Second Place Prize for design contest) NetFPGA Developers Workshop, Stanford University, CA, August, 2010.
Caliper: Precise and Responsive Traffic Generation using NetThreads (poster and short paper), (pdf) "Monia Ghobadi, Martin Labrecque, Geoffrey Salmon, Kaveh Aasaraai, ACM Special Interest Group on Data Communications Conference, New Delhi, India, August, 2010.
Caliper: A Tool to Generate Precise and Closed-loop Traffic, (pdf) Monia Ghobadi, Martin Labrecque, Geoff Salmon, Kaveh Aasaari, Soheil Yeganeh, Yashar Ganjali, and J. Gregory Steffan, SIGCOMM, demo paper, New Delhi, India, August, 2010.
DART: Fast and Flexible FPGA-Based NoC Simulation, (pdf) Danyao Wang, Natalie Enright Jerger, and J. Gregory Steffan, Workshop on Architectural Research Prototyping, Saint Malo, France, June, 2010.
A GPU-Inspired Soft Processor for High-Throughput Acceleration, (pdf) Jeffrey Kingyens and J. Gregory Steffan, Reconfigurable Architectures Workshop, Atlanta, GA, April, 2010.
SmartData: Make the data think for itself, George J. Tomko, Donald S. Borrett, Hon C. Kwan, and Greg Steffan, Springer: Identity in the Information Society, April, 2010.
Application-Specific Signatures for Transactional Memory in Soft Processors, (pdf, ppt) Martin Labrecque, Mark Jeffrey, and J. Gregory Steffan, International Symposium on Applied Reconfigurable Computing, (Best Paper Award), Bangkok, Thailand, March, 2010.
Efficient Multi-Ported Memories for FPGAs, (pdf, ppt) Eric LaForest and J. Gregory Steffan, International Symposium on Field-Programmable Gate Arrays, Selected as one of the top 25 papers in the first 20 years of the conference, Monterey, CA, February, 2010.
Fine-Grain Performance Scaling of Soft Vector Processors, (pdf, ppt) Peter Yiannacouras, J. Gregory Steffan, and Jonathan Rose, International Conference on Compilers, Architecture and Synthesis for Embedded Systems, Grenoble, France, October, 2009.
Efficient Multi-Ported Memories for FPGAs, (pdf) Eric LaForest, Masters Thesis, Department of Electrical and Computer Engineering, University of Toronto, September, 2009.
FPGA-Based Soft Vector Processors, (pdf) Peter Yiannacouras, Ph.D. Thesis, Department of Electrical and Computer Engineering, University of Toronto, September, 2009.
NetFPGA-based Precise Traffic Generation, (pdf) Geoff Salmon, Monia Ghobadi, Yashar Ganjali, Martin Labrecque, and J. Gregory Steffan, in NetFPGA Developers Workshop, Stanford University, CA, August, 2009.
Fast Critical Sections via Thread Scheduling for FPGA-based Multithreaded Processors, (pdf, ppt) Martin Labrecque and J. Gregory Steffan, in International Conference on Field Programmable Logic and Applications, Prague, Czech Republic, August, 2009.
NetThreads: Programming NetFPGA with Threaded Software, (pdf, ppt) Martin Labrecque, J. Gregory Steffan, Geoff Salmon, Monia Ghobadi, and Yashar Ganjali, in NetFPGA Developers Workshop, Stanford University, CA, August, 2009.
Data Parallel FPGA Workloads: Software Versus Hardware, (pdf, ppt) Peter Yiannacouras, J. Gregory Steffan, and Jonathan Rose, International Conference on Field Programmable Logic and Applications, (Nominated for Servit best paper award), Prague, Czech Republic, August, 2009.
Tolerating Delinquent Loads with Speculative Execution, Chuck Zhao, J. Gregory Steffan, Cristiana Amza, and Allan Kielstra, Workshop on Parallel Execution of Sequential Programs on Multi-core Architectures, Austin, TX, June, 2009.
Compiler-Based Checkpointing and the Potential for Tolerating Delinquent Loads, (pdf) Chuck (Chengyan) Zhao, Greg Steffan, and Cristiana Amza, University of Toronto, (UT-EECG-TR-2009-0017) April, 2009.
Soft Vector Processors vs FPGA Custom Hardware: Measuring and Reducing the Gap (poster), (pdf) Peter Yiannacouras, J. Gregory Steffan and Jonathan Rose, International Symposium on Field-Programmable Gate Arrays, Monterey, CA, February, 2009.
Improving Memory System Performance for Soft Vector Processors, (pdf, ppt) Peter Yiannacouras, J. Gregory Steffan, and Jonathan Rose, Workshop on Soft Processor Systems, Toronto, ON, October, 2008.
A GPU-Like Soft Processor for High-Throughput Acceleration, (pdf, ppt) Jeffrey Kingyens and J. Gregory Steffan, Workshop on Soft Processor Systems, Toronto, ON, October, 2008.
VESPA: Portable, Scalable, and Flexible FPGA-Based Vector Processors, (pdf, ppt) Peter Yiannacouras, J. Gregory Steffan, and Jonathan Rose, International Conference on Compilers, Architecture and Synthesis for Embedded Systems, Atlanta, GA, October, 2008.
A GPU-Inspired Soft Processor for High-Throughput Acceleration, (pdf) Jeffrey Kingyens, Masters Thesis, Department of Electrical and Computer Engineering, University of Toronto, September, 2008.
Compiler and Hardware Support for Reducing the Synchronization of Speculative Threads, (pdf) Antonia Zhai, J. Gregory Steffan, Christopher B. Colohan, and Todd C. Mowry, ACM Transactions on Architecture and Code Optimization, 5 (1) May, 2008.
Scaling Soft Processor Systems, (pdf, ppt) Martin Labrecque, Peter Yiannacouras and J. Gregory Steffan, IEEE Symposium on Field-Programmable Custom Computing Machines, Palo Alto, CA, April, 2008.
The Potential for Variable-Granularity Access Tracking for Optimistic Parallelism, (pdf, ppt) Mihai Burcea, J. Gregory Steffan and Cristiana Amza, ACM SIGPLAN Workshop on Memory Systems Performance and Correctness (in conjunction with ASPLOS), Seattle, WA, March, 2008.
Incrementally Parallelizing Database Transactions with Thread-Level Speculation, (pdf) Christopher B. Colohan, Anastassia Ailamaki, J. Gregory Steffan, and Todd C. Mowry, ACM Transactions on Computer Systems, 26 (1) February, 2008.
Lengthening Traces to Improve Opportunities for Dynamic Optimization, (pdf, ppt) Chuck Zhao, Youfeng Wu, J. Gregory Steffan and Cristiana Amza, 12th Workshop on Interaction between Compilers and Computer Architectures (in conjuntion with HPCA), Salt Lake City, UT, February, 2008.
A Dynamic Instrumentation Approach to Software Transactional Memory, (pdf) Marek Olszewski, Masters Thesis, Department of Electrical and Computer Engineering, University of Toronto, October, 2007.
JudoSTM: a Dynamic Binary Rewriting Approach to Software Transactional Memory, (pdf, ppt) Marek Olszewski, Jeremy Cutler and J. Gregory Steffan, International Conference on Parallel Architectures and Compilation Techniques, Brasov, Romania, September, 2007.
Improving Pipelined Soft Processors with Multithreading, (pdf, ppt) Martin Labrecque and J. Gregory Steffan, International Conference on Field-Programmable Logic, Reconfigurable Computing, and Applications, Amsterdam, Netherlands, August, 2007.
CMP Support for Large and Dependent Speculative Threads, (pdf) Christopher B. Colohan, Anastassia Ailamaki, J. Gregory Steffan, and Todd C. Mowry, IEEE Transactions on Parallel and Distributed Systems, 18 (8) August, 2007.
Custom Code Generation for Soft Processors, (pdf) Martin Labrecque, Peter Yiannacouras and J. Gregory Steffan, SIGARCH Computer Architecture News, 35 (3) June, 2007.
Exploration and Customization of FPGA-Based Soft Processors, (pdf) Peter Yiannacouras, J. Gregory Steffan, and Jonathan Rose, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems---special issue on FPGAs, 26 (2) February, 2007.
Custom Code Generation for Soft Processors, (pdf, ppt) Martin Labrecque, Peter Yiannacouras and J. Gregory Steffan, Reconfigurable and Adaptive Architecture Workshop (in conjunction with MICRO), Orlando, FA, December, 2006.
A Probabilistic Pointer Analysis for Speculative Optimizations, (pdf, ppt) Jeffrey Da Silva and J. Gregory Steffan, International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, CA, October, 2006.
Scaling Task Graphs for Network Processors, Martin Labrecque and J. Gregory Steffan, IFIP International Conference on Network and Parallel Computing, Tokyo, Japan, October, 2006.
Tolerating Dependences Between Large Speculative Threads Via Sub-Threads, (pdf, ppt) Christopher B. Colohan, Anastassia Ailamaki, J. Gregory Steffan, and Todd C. Mowry, International Symposium on Computer Architecture, Boston, MA, June, 2006.
Scaling Task Graphs for Network Processors, Martin Labrecque and J. Gregory Steffan, Conference for Languages, Compilers, and Tools for Embedded Systems (poster and abstract), Ottawa, Ontario, Canada, June, 2006.
Improving Cache Locality for Thread-Level Speculation, (pdf, ppt) Stanley Fung and J. Gregory Steffan, IEEE International Parallel and Distributed Processing Symposium, Rhodes Island, Greece, April, 2006.
A Probabilistic Pointer Analysis for Speculative Optimizations, (pdf) Jeffrey Da Silva, Masters Thesis, Department of Electrical and Computer Engineering, University of Toronto, March, 2006.
Application-Specific Customization of Soft Processor Microarchitecture, (pdf, ppt) Peter Yiannacouras, J. Gregory Steffan, and Jonathan Rose, International Symposium on Field-Programmable Gate Arrays, Monterey, CA, February, 2006.
Towards a Compilation Infrastructure for Network Processors, (pdf) Martin Labrecque, Masters Thesis, Department of Electrical and Computer Engineering, University of Toronto, January, 2006.
Improving Cache Locality for Thread-Level Speculation, (pdf) Stanley Fung, Masters Thesis, Department of Electrical and Computer Engineering, University of Toronto, September, 2005.
Optimistic Intra-Transaction Parallelism on Chip Multiprocessors, (pdf, ppt) Christopher B. Colohan, Anastassia Ailamaki, J. Gregory Steffan, and Todd C. Mowry, International Conference on Very Large Data Bases, Trondheim, Norway, September, 2005.
The Microarchitecture of FPGA-Based Soft Processors, (pdf) Peter Yiannacouras, Masters Thesis, Department of Electrical and Computer Engineering, University of Toronto, September, 2005.
The Microarchitecture of FPGA-Based Soft Processors, (pdf, ppt) Peter Yiannacouras, Jonathan Rose and J. Gregory Steffan, International Conference on Compilers, Architecture and Synthesis for Embedded Systems, San Francisco, CA, September, 2005.
The STAMPede Approach to Thread-Level Speculation, (pdf) J. Gregory Steffan, Christopher B. Colohan, Antonia Zhai, and Todd C. Mowry, ACM Transactions on Computer Systems, 23 (3) August, 2005.
Supporting Large Speculative Threads for Databases and Beyond, (pdf) "Christopher B. Colohan, Anastassia Ailamaki, J. Gregory Steffan and Todd C. Mowry, School of Computer Science, Carnegie Mellon University, (CMU-CS-05-109) July, 2005.
Optimistic Intra-Transaction Parallelism on Chip Multiprocessors, (pdf) Christopher B. Colohan, Anastassia Ailamaki, J. Gregory Steffan and Todd C. Mowry, School of Computer Science, Carnegie Mellon University, (CMU-CS-05-118) March, 2005.
SPREE: Microarchitectural Exploration on FPGAs, Peter Yiannacouras, J. Gregory Steffan and Jonathan Rose, Workshop on Architecture Research using FPGA Platforms (poster), San Francisco, CA, February, 2005.
Compiler Optimization of Memory-Resident Value Communication Between Speculative Threads, (pdf, ppt) Antonia Zhai, Christopher B. Colohan, J. Gregory Steffan, and Todd C. Mowry, International Symposium on Code Generation and Optimization, Palo Alto, CA, March, 2004.
Hardware Support for Thread-Level Speculation, (pdf) J. Gregory Steffan, Ph.D. Thesis, School of Computer Science, Carnegie Mellon University, (CMU-CS-03-122) April, 2003.
Compiler Optimization of Scalar Value Communication Between Speculative Threads, (pdf, ppt) Antonia Zhai, Christopher B. Colohan, J. Gregory Steffan, and Todd C. Mowry, International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, CA, October, 2002.
Improving Value Communication for Thread-Level Speculation, (pdf, ppt) J. Gregory Steffan, Christopher B. Colohan, Antonia Zhai, and Todd C. Mowry, International Symposium on High-Performance Computer Architecture, Cambridge, MA, February, 2002.
Generating Network Topologies That Obey Power Laws, (pdf, ppt) Christopher R. Palmer and J. Gregory Steffan, Global Internet Symposium, San Francisco, CA, November, 2000.
- Network Topology Generator Software: README; PLODD source code; Recursive source code;
A Scalable Approach to Thread-Level Speculation, (pdf, ppt) J. Gregory Steffan, Christopher B. Colohan, Antonia Zhai, and Todd C. Mowry, International Symposium on Computer Architecture, Vancouver, BC, June, 2000.
Secure Sharing with Satan's File System, (pdf) Chris Colohan, Chuck Rosenberg, and J. Gregory Steffan, Selected Reports: Fall 1997 Software Systems Course, G. Gibson (ed.), School of Computer Science, Carnegie Mellon University, (CMU-CS-98-103) April, 1998.
The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization, (pdf, slides.pdf) J. Gregory Steffan and Todd C. Mowry, International Symposium on High-Performance Computer Architecture, Las Vegas, NV, February, 1998.
Architectural Support for Thread-Level Data Speculation, (ps.gz) J. Gregory Steffan, Christopher B. Colohan, and Todd C. Mowry, School of Computer Science, Carnegie Mellon University, (CMU-CS-97-188) November, 1997.
The Potential for Thread-Level Data Speculation in Tightly-Coupled Multiprocessors, (pdf) J. Gregory Steffan, Masters Thesis, Department of Electrical and Computer Engineering, University of Toronto, February, 1997.