ECE1718H Spring 2003:
Special Topics in Computer Hardware Design
Homework
There will be three homeworks (during the first phase of the course) which
provide hands-on experience with architectural simulation of the mechanisms
described in class, as well as preparation for the project.
Tentative homework schedule:
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Homework 1:
Measuring maximum instruction-level parallelism. Out: Jan 22; due: Feb 5; worth: 9%.
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Homework 2:
Adding a memory model to homework 1. Out: Feb 5; due: Feb 12; worth: 7%.
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Homework 3:
Parallelizing a simple program. Out: Feb 12; due: Mar 5; worth: 9%.
Corrections to homework 1:
- The expected IPC for compress95 should be 20.2 and 8.2 without and
with control dependences respectively.
- Instruction counts and IPC may vary by a percent or so, due to
simplescalar's sensitivity to your environment and the system---hence an exact
match in counts is not required.